3
LRESETNMIEN
CORESEL[2:0]/
/LRESET
NMI
1 2
66AK2L06
SPRS930 –APRIL 2015
www.ti.com
Table 11-46. NMI and LRESET Timing Requirements
(1)
(continued)
(see Figure 11-42)
NO. MIN MAX UNIT
2 th( LRESETNMIEN - LRESET ) Hold time - LRESET valid after LRESETNMIEN high 12*P ns
2 th( LRESETNMIEN - NMI ) Hold time - NMI valid after LRESETNMIEN high 12*P ns
2 th( LRESETNMIEN -CORESELn) Hold time - CORESEL[2:0] valid after LRESETNMIEN high 12*P ns
3 tw( LRESETNMIEN ) Pulsewidth - LRESETNMIEN low width 12*P ns
Figure 11-42. NMI and LRESET Timing
11.10 On-Chip Standalone RAM (OSR)
The 1MB OSR is added to the device for:
• QM External Linking RAM
• NetCP1.5 intermediate data buffer
• Intermediate buffering of other data storage
The OSR supported features include:
• SRAM supports ECC with Read-Modify-Write logic
• RTA memory
• Support interrupt for ECC error event
• Support Little and Big-endian modes of operation
OSR does not support any type of cache access, hence this memory space must always be marked as
non-cacheable region for both DSP and ARM cores.
11.11 DDR3A Memory Controller
The 72-bit DDR3 Memory Controller bus of the 66AK2L06 is used to interface to JEDEC standard-
compliant DDR3 SDRAM devices. The DDR3 external bus interfaces only to DDR3 SDRAM devices and
does not share the bus with any other type of peripheral.
11.11.1 DDR3 Memory Controller Device-Specific Information
The 66AK2L06 includes one 64-bit wide, 1.5-V DDR3 SDRAM EMIF interface. The DDR3 interface can
operate at 800 mega transfers per second (MTS), 1033 MTS, 1333 MTS, and 1600 MTS.
Due to the complicated nature of the interface, a limited number of topologies are supported to provide a
16-bit, 32-bit, or 64-bit interface.
The DDR3 electrical requirements are fully specified in the DDR JEDEC Specification JESD79-3C.
Standard DDR3 SDRAMs are available in 8-bit and 16-bit versions allowing for the following bank
topologies to be supported by the interface:
• 72-bit: Five 16-bit SDRAMs (including 8 bits of ECC)
• 72-bit: Nine 8-bit SDRAMs (including 8 bits of ECC)
• 36-bit: Three 16-bit SDRAMs (including 4 bits of ECC)
258 66AK2L06 Peripheral Information and Electrical Specifications Copyright © 2015, Texas Instruments Incorporated
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