66AK2L06
SPRS930 –APRIL 2015
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Table 11-40. 66AK2L06 to JESD204B Signal Name
Cross Reference
66AK2L06 JESD204B
DFESYNCIN 0 and 1 SYNCIN
DFESYNCOUT 0 and 1 SYNCOUT
DFESYSREF SYSREF
SYSCLK SYSCLK
Table 11-41. DFEIO (0-17) GPIO Input Pulse Timing Requirements
(see Figure 11-39)
NO. PARAMETER MIN MAX UNIT
2 tw(DFEGPIL) Pulse Duration, DFEGPI Low 2P
(1)
ns
1 tw(DFEGPIH) Pulse Duration, DFEGPI High 2P ns
(1) P = 1/SYSCLK clock frequency in ns.
Table 11-42. DFEIO (0-17) GPIO Output Timing Characteristics
(see Figure 11-39)
NO. PARAMETER MIN MAX UNIT
4 tw(DFEGPOL) Pulse Duration, DFEGPO Low 2P
(1)
ns
3 tw(DFEGPOH) Pulse Duration, DFEGPO High 2P ns
(1) P = 1/SYSCLK clock frequency in ns.
Figure 11-39. DFEIO (0-17) GPIO Input/Output
Table 11-43. DFESYNCIN Sync Input Pulse Timing Requirements
(see Figure 11-40)
NO. PARAMETER MIN MAX UNIT
2 tw(DFESYNCINN0L) Pulse Duration, DFESYNCIN(N)0 Low 2P
(1)
ns
1 tw(DFESYNCINN0H) Pulse Duration, DFESYNCIN(N)0 High 2P ns
2 tw(DFESYNCINP0L) Pulse Duration, DFESYNCIN(P)0 Low 2P ns
1 tw(DFESYNCINP0H) Pulse Duration, DFESYNCIN(P)0 High 2P ns
2 tw(DFESYNCINN1L) Pulse Duration, DFESYNCIN(N)1 Low 2P ns
1 tw(DFESYNCINN1H) Pulse Duration, DFESYNCIN(N)1 High 2P ns
2 tw(DFESYNCINP1L) Pulse Duration, DFESYNCIN(P)1 Low 2P ns
1 tw(DFESYNCINP1H) Pulse Duration, DFESYNCIN(P)1 High 2P ns
(1) P = 1/SYSCLK clock frequency in ns.
Table 11-44. DFESYNCOUTSync Output Pulse Switching Characteristics
(see Figure 11-40)
NO. PARAMETER MIN MAX UNIT
2 tw(DFESYNCOUTN0L) Pulse Duration, DFESYNCOUT(N)0 Low 2P
(1)
ns
1 tw(DFESYNCOUTN0H) Pulse Duration, DFESYNCOUT(N)0 High 2P ns
(1) P = 1/SYSCLK clock frequency in ns.
256 66AK2L06 Peripheral Information and Electrical Specifications Copyright © 2015, Texas Instruments Incorporated
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