66AK2L06
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SPRS930 –APRIL 2015
11.8.2 DFE Clock Divider Control Register (DFE_CLKDIV_CTL)
The DFE_CLKDIV_CTL register is used to program the clock divider that exists at the chip level, it divides
down the output of the clock signal from the DFE PLL Controller and is routed to the DFE subsytem core
logic.
Figure 11-37. DFE Clock Divider Control Register (DFE_CLKDIV_CTL)
31 2 1 0
Reserved DIV_MODE
R-0 RW-00
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-38. DFE Clock Divider Control Register Field Descriptions
Bit Field Description
31-2 Reserved
1-0 DIV_MODE A 2-bit field that selects the values for the reference divider
• 00 = DFE PLL output clock divided by 4 (default)
• 01 = DFE PLL output clock divided by 2
• 10 = DFE PLL output clock divided by2
• 11 = Reserved
11.8.3 DFE Clock Sync Control Register (DFE_CLKSYNC_CTL)
The DFE_CLKSYNC_CTL register is used to enable the SYSCLK and SYSREF synchronization logic.
Synchronous Ethernet (SyncE) allows distribution of traceable frequency synchronization to packet nodes
the need to communication with TDM network elements. It is also used to distribute timing to applications
that rely on precise frequency synchronization such as wireless backhaul.
In 66AK2L06, SyncE is achieved by deriving a TSRXCLKOUTn clock signal based on recovered RX clock
from the SGMII SerDes interface. The TSRXCLKOUTn is fed into an DPLL which will supply, along with a
clock generator, TSREFCLK, SGMII, SYSCLK, and SYSREF clocks. SyncE may also be achieved by
software PLL, via reading registers from CPTS, then drive a clock adjusting signal via SPI (similar to IEEE
1588 clock adjusting method).
Figure 11-38. DFE Clock Sync Control Register (DFE_CLKSYNC_CTL)
31 1 0
Reserved SYNC_EN
R-0 RW-0
Legend: RW = Read/Write; - n = value after reset
Table 11-39. DFE Clock Sync Control Register Field Descriptions
Bit Field Description
31-1 Reserved
0 SYNC_EN Sync logic enable
• 0 = Sync logic not enabled (default)
• 1 = Sync logic enabled
11.8.4 DFE Electrical Data/Timing
Table 11-40 provides a cross reference between the JESD204B signal names and the 66AK2L06 name.
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