66AK2L06
SPRS930 –APRIL 2015
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11.8.1 DFE PLL Control Registers
The DFE PLL, which is used to drive the DFE and IQN, does not use a PLL controller. DFE PLL can be
controlled using the DFEPLLCTL0 and DFEPLLCTL1 registers located in the Bootcfg module. These
MMRs (memory-mapped registers) exist inside the Bootcfg space. To write to these registers, software
must go through an unlocking sequence using the KICK0 and KICK1 registers. For suggested
configuration values, see Section 9.1.3.1. See Section 9.2.3.5 for the address location of the registers and
locking and unlocking sequences for accessing these registers. These registers are reset on POR only.
Figure 11-35. DFE PLL Control Register 0 (DFEPLLCTL0)
31 24 23 22 19 18 6 5 0
BWADJ[7:0] BYPASS CLKOD PLLM PLLD
RW-0000 1001 RW-1 RW-0001 RW-0000000010011 RW-000000
Legend: RW = Read/Write; -n = value after reset
Table 11-36. DFE PLL Control Register 0 Field Descriptions (DFEPLLCTL0)
Bit Field Description
31-24 BWADJ[7:0] BWADJ[11:8] and BWADJ[7:0] are located in DFEPLLCTL0 and DFEPLLCTL1 registers. BWADJ[11:0] should
be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ = ((PLLM+1)>>1) - 1.
23 BYPASS PLL bypass mode:
• 0 = PLL is not in BYPASS mode
• 1 = PLL is in BYPASS mode
22-19 CLKOD A 4-bit field that selects the values for the PLL post divider. Valid post divider values are 1 and even values
from 2 to 16. CLKOD field is loaded with output divide value minus 1
18-6 PLLM A 13-bit field that selects the values for the multiplication factor (see note below). PLLM field is loaded with the
multiply factor minus 1.
5-0 PLLD A 6-bit field that selects the values for the reference divider. PLLD field is loaded with reference divide value
minus 1.
Figure 11-36. DFE PLL Control Register 1 (DFEPLLCTL1)
31 15 14 13 12 7 6 5 4 3 0
Reserved PLLRST DFEPLL Reserved ENSAT Reserved BWADJ[11:8]
RW - 00000000000000000 RW-0 RW-0 RW-000000 RW-0 R-00 RW- 0000
Legend: RW = Read/Write; - n = value after reset
Table 11-37. DFE PLL Control Register 1 Field Descriptions (DFEPLLCTL1)
Bit Field Description
31-15 Reserved Reserved
14 PLLRST PLL Reset bit
• 0 = PLL Reset is released
• 1 = PLL Reset is asserted
13 DFEPLL
• 0 = Not supported
• 1 = DFEPLL
12-7 Reserved Reserved
6 ENSAT Needs to be set to 1 for proper PLL operation
5-4 Reserved Reserved
3-0 BWADJ[11:8] BWADJ[11:8] and BWADJ[7:0] are located in DFEPLLCTL0 and DFEPLLCTL1 registers. BWADJ[11:0] should
be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ = ((PLLM+1)>>1) - 1.
254 66AK2L06 Peripheral Information and Electrical Specifications Copyright © 2015, Texas Instruments Incorporated
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