NETCP
NETCP
PLLOUT
PLLD
VCO
PLLM
NETCP PLL
CLKOD
INTBYPASS
0
1
SYSCLK(N|P)
ALTCORECLK(N|P)
DDR3CLK
CORECLKSEL[1:0]
/n
PLLSEL
PLLCTL_SYSCLK
1
0
BYPASS
0
1
66AK2L06
SPRS930 –APRIL 2015
www.ti.com
11.7 NETCP PLL
The NETCP PLL generates interface clocks for the Network Coprocessor. Like Main PLL and ARM PLL,
using the CORECLKSEL[1:0] pins the user can select the input source of the NETCP PLL. When coming
out of power-on reset, NETCP PLL comes out in a bypass mode and needs to be programmed to a valid
frequency before being enabled and used.
NETCP PLL power is supplied via the NETCP PLL power-supply pin (AVDDA3). An external EMI filter
circuit must be added to all PLL supplies. See the Hardware Design Guide for KeyStone II Devices
application report (SPRABV0) for detailed recommendations.
Figure 11-32. NETCP PLL Block Diagram
11.7.1 NETCP PLL Local Clock Dividers
The clock signal from the NETCP PLL Controller is routed to the Network Coprocessor. The NETCP
module has two internal dividers with fixed division ratios. See table Table 11-34.
11.7.2 NETCP PLL Control Registers
The NETCP PLL, which is used to drive the Network Coprocessor, does not use a PLL controller. NETCP
PLL can be controlled using the NETCPPLLCTL0 and NETCPPLLCTL1 registers located in the Bootcfg
module. These MMRs (memory-mapped registers) exist inside the Bootcfg space. To write to these
registers, software must go through an unlocking sequence using the KICK0 and KICK1 registers. For
suggested configuration values, see Section 9.1.3. See Section 9.2.3.5 for the address location of the
registers and locking and unlocking sequences for accessing these registers. These registers are reset on
POR only.
Figure 11-33. NETCP PLL Control Register 0 (NETCPPLLCTL0)
31 24 23 22 19 18 6 5 0
BWADJ[7:0] BYPASS CLKOD PLLM PLLD
RW,+0000 1001 RW,+0 RW,+0001 RW,+0000000010011 RW,+000000
Legend: RW = Read/Write; -n = value after reset
Table 11-34. NETCP PLL Control Register 0 Field Descriptions (NETCPPLLCTL0)
Bit Field Description
31-24 BWADJ[7:0] BWADJ[11:8] and BWADJ[7:0] are located in NETCPPLLCTL0 and NETCPPLLCTL1 registers. BWADJ[11:0]
should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ =
((PLLM+1)>>1) - 1.
23 BYPASS Enable bypass mode
• 0 = Bypass disabled
• 1 = Bypass enabled
22-19 CLKOD A 4-bit field that selects the values for the PLL post divider. Valid post divider values are 1 and even values
from 2 to 16. CLKOD field is loaded with output divide value minus 1
252 66AK2L06 Peripheral Information and Electrical Specifications Copyright © 2015, Texas Instruments Incorporated
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