66AK2L06
SPRS930 –APRIL 2015
www.ti.com
Table 11-30. Main PLL Controller/ARM/DFE/PCIe/Shared SerDes/USB/TSREF Clock Input Timing
Requirements
(1)
(continued)
(see Figure 11-24 through Figure 11-27)
NO. MIN MAX UNIT
4 tf(SHARED_SERDES_0_ Fall time SHARED_SERDES_0_REFCLK[P:N] 0.2*tc(SHARED_SERDES
ps
REFCLK[P:N]) differential fall time (10% to 90%) _0_REFCLK[P:N])
5 tj(SHARED_SERDES_0_ Jitter, RMS SHARED_SERDES_0_REFCLKN
4 ps, RMS
REFCLKN)
5 tj(SHARED_SERDES_0_ Jitter, RMS SHARED_SERDES_0_REFCLKP
4 ps, RMS
REFCLKP)
SHARED_SERDES_1_REFCLK[P:N]
1 tc(SHARED_SERDES_1_ Cycle time SHARED_SERDES_1_REFCLKN
8.138 ns
REFCLKN) cycle time
1 tc(SHARED_SERDES_1_ Cycle time SHARED_SERDES_1_REFCLKP
8.138 ns
REFCLKP) cycle time
3 tw(SHARED_SERDES_1_ Pulse width SHARED_SERDES_1_REFCLKN 0.45*tc(SHARED_ 0.55*tc(SHARED_
ns
REFCLKN) high SERDES_1_REFCLKN) SERDES_1_REFCLKN)
2 tw(SHARED_SERDES_1_ Pulse width SHARED_SERDES_1_REFCLKN 0.45*tc(SHARED_ 0.55*tc(SHARED_
ns
REFCLKN) low SERDES_1_REFCLKN) SERDES_1_REFCLKN)
2 tw(SHARED_SERDES_1_ Pulse width SHARED_SERDES_1_REFCLKP 0.45*tc(SHARED_ 0.55*tc(SHARED_
ns
REFCLKP) high SERDES_1_REFCLKP) SERDES_1_REFCLKP)
3 tw(SHARED_SERDES_1_ Pulse width SHARED_SERDES_1_REFCLKP 0.45*tc(SHARED_ 0.55*tc(SHARED_
ns
REFCLKP) low SERDES_1_REFCLKP) SERDES_1_REFCLKP)
4 tr(SHARED_SERDES_1_ Rise time SHARED_SERDES_1_REFCLK 0.2*tc(SHARED_SERDES
ps
REFCLK[P:N]) differential rise time (10% to 90%) _1_REFCLK[P:N])
4 tf(SHARED_SERDES_1_ Fall time CSISC2_0REFCLK differential fall time 0.2*tc(SHARED_SERDES
ps
REFCLK[P:N]) (10% to 90%) _1_REFCLK[P:N])
5 tj(CSISC2_0REFCLKN) Jitter, RMS CSISC2_0REFCLKN 4 ps, RMS
5 tj(CSISC2_0REFCLKP) Jitter, RMS CSISC2_0REFCLKP 4 ps, RMS
USBCLK[P:M]
1 tc(USBCLKN) Cycle time USBCLKN cycle time 10 10 ns
1 tc(USBCLKP) Cycle time USBCLKP cycle time 10 10 ns
3 tw(USBCLKN) Pulse width USBCLKN high 0.45*tc(USBCLKN) 0.55*tc(USBCLKN) ns
2 tw(USBCLKN) Pulse width USBCLKN low 0.45*tc(USBCLKN) 0.55*tc(USBCLKN) ns
2 tw(USBCLKP) Pulse width USBCLKP high 0.45*tc(USBCLKP) 0.55*tc(USBCLKP) ns
3 tw(USBCLKP) Pulse width USBCLKP low 0.45*tc(USBCLKP) 0.55*tc(USBCLKP) ns
4 tr(USBCLK[P:M]) Rise time USBCLK[P:M] differential rise time
75 500 ps
(10% to 90%)
4 tf(USBCLK[P:M]) Fall time USBCLK[P:M] differential fall time (10%
75 500 ps
to 90%)
5 tj(USBCLKN) Jitter, RMS USBCLKN 3 ps, RMS
5 tj(USBCLKP) Jitter, RMS USBCLKP 3 ps, RMS
TSREFCLK[P:N]
(3)
1 tc(TSREFCLKN) Cycle time TSREFCLKN cycle time 3.25 32.55 ns
1 tc(TSREFCLKP) Cycle time TSREFCLKP cycle time 3.25 32.55 ns
3 tw(TSREFCLKN) Pulse width TSREFCLKN high 0.45*tc(TSREFCLKN) 0.55*tc(TSREFCLKN) ns
2 tw(TSREFCLKN) Pulse width TSREFCLKN low 0.45*tc(TSREFCLKN) 0.55*tc(TSREFCLKN) ns
2 tw(TSREFCLKP) Pulse width TSREFCLKP high 0.45*tc(TSREFCLKP) 0.55*tc(TSREFCLKP) ns
3 tw(TSREFCLKP) Pulse width TSREFCLKP low 0.45*tc(TSREFCLKP) 0.55*tc(TSREFCLKP) ns
4 tr(TSREFCLK[P:N]) Rise time TSREFCLK differential rise time (10%
50 350 ps
to 90%)
4 tf(TSREFCLK[P:N]) Fall time TSREFCLK differential fall time (10% to
50 350 ps
90%)
5 tj(TSREFCLKN) Jitter, RMS TSREFCLKN 5.8 ps, RMS
5 tj(TSREFCLKP) Jitter, RMS TSREFCLKP 5.8 ps, RMS
(3) TSREFCLK clock input is LVDS compliant
248 66AK2L06 Peripheral Information and Electrical Specifications Copyright © 2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: 66AK2L06