66AK2L06
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SPRS930 –APRIL 2015
Table 11-30. Main PLL Controller/ARM/DFE/PCIe/Shared SerDes/USB/TSREF Clock Input Timing
Requirements
(1)
(continued)
(see Figure 11-24 through Figure 11-27)
NO. MIN MAX UNIT
ALTCORECLK[P:N]
1 tc(ALTCORCLKN) Cycle time ALTCORECLKN cycle time 3.2 25 ns
1 tc(ALTCORECLKP) Cycle time ALTCORECLKP cycle time 3.2 25 ns
3 tw(ALTCORECLKN) Pulse width ALTCORECLKN high 0.45*tc(ALTCORECLKN) 0.55*tc(ALTCORECLKN) ns
2 tw(ALTCORECLKN) Pulse width ALTCORECLKN low 0.45*tc(ALTCORECLKN) 0.55*tc(ALTCORECLKN) ns
2 tw(ALTCORECLKP) Pulse width ALTCORECLKP high 0.45*tc(ALTCORECLKP) 0.55*tc(ALTCORECLKP) ns
3 tw(ALTCORECLKP) Pulse width ALTCORECLKP low 0.45*tc(ALTCORECLKP) 0.55*tc(ALTCORECLKP) ns
4 tr(ALTCORECLK_200 mV) Transition time ALTCORECLK differential rise
50 350 ps
time (200 mV)
4 tf(ALTCORECLK_200 mV) Transition time ALTCORECLK differential fall
50 350 ps
time (200 mV)
5 tj(ALTCORECLKN) Jitter, peak_to_peak _ periodic ALTCORECLKN 100 ps
5 tj(ALTCORECLKP) Jitter, peak_to_peak _ periodic ALTCORECLKP 100 ps
SGMIICLK[P:N]
1 tc(SGMIICLKN) Cycle time SGMIICLKN cycle time 6.4 ns
1 tc(SGMIICLKP) Cycle time SGMIICLKP cycle time 6.4 ns
3 tw(SGMIICLKN) Pulse width SGMIICLKN high 0.45*tc(SGMIICLKN) 0.55*tc(SGMIICLKN) ns
2 tw(SGMIICLKN) Pulse width SGMIICLKN low 0.45*tc(SGMIICLKN) 0.55*tc(SGMIICLKN) ns
2 tw(SGMIICLKP) Pulse width SGMIICLKP high 0.45*tc(SGMIICLKP) 0.55*tc(SGMIICLKP) ns
3 tw(SGMIICLKP) Pulse width SGMIICLKP low 0.45*tc(SGMIICLKP) 0.55*tc(SGMIICLKP) ns
4 tr(SGMIICLK_250mV) Transition time SGMIICLK differential rise time
50 350 ps
(250 mV)
4 tf(SGMIICLK_250mV) Transition time SGMIICLK differential fall time
50 350 ps
(250 mV)
5 tj(SGMIICLKN) Jitter, RMS SGMIICLKN 8 ps, RMS
5 tj(SGMIICLKP) Jitter, RMS SGMIICLKP 8 ps, RMS
PCIECLK[P:N]
1 tc(PCIECLKN) Cycle time PCIECLKN cycle time 10 ns
1 tc(PCIECLKP) Cycle time PCIECLKP cycle time 10 ns
3 tw(PCIECLKN) Pulse width PCIECLKN high 0.45*tc(PCIECLKN) 0.55*tc(PCIECLKN) ns
2 tw(PCIECLKN) Pulse width PCIECLKN low 0.45*tc(PCIECLKN) 0.55*tc(PCIECLKN) ns
2 tw(PCIECLKP) Pulse width PCIECLKP high 0.45*tc(PCIECLKP) 0.55*tc(PCIECLKP) ns
3 tw(PCIECLKP) Pulse width PCIECLKP low 0.45*tc(PCIECLKP) 0.55*tc(PCIECLKP) ns
4 tr(PCIECLK[P:N]) Rise time PCIECLK[P:N] differential rise time
0.2*tc(PCIECLK[P:N]) ps
(10% to 90%)
4 tf(PCIECLK[P:N]) Fall time PCIECLK[P:N] differential fall time (10%
0.2*tc(PCIECLK[P:N]) ps
to 90%)
5 tj(PCIECLKN) Jitter, RMS PCIECLKN 4 ps, RMS
5 tj(PCIECLKP) Jitter, RMS PCIECLKP 4 ps, RMS
SHARED_SERDES_0_REFCLK[P:N]
1 tc(SHARED_SERDES_0_ Cycle time SHARED_SERDES_0_REFCLKN
8.138 ns
REFCLKN) cycle time
1 tc(SHARED_SERDES_0_ Cycle time SHARED_SERDES_0_REFCLKP
8.138 ns
REFCLKP) cycle time
3 tw(SHARED_SERDES_0_ Pulse width SHARED_SERDES_0_REFCLKN 0.45*tc(SHARED_ 0.55*tc(SHARED_
ns
REFCLKN) high SERDES_0_REFCLKN) SERDES_0_REFCLKN)
2 tw(SHARED_SERDES_0_ Pulse width SHARED_SERDES_0_REFCLKN 0.45*tc(SHARED_ 0.55*tc(SHARED_
ns
REFCLKN) low SERDES_0_REFCLKN) SERDES_0_REFCLKN)
2 tw(SHARED_SERDES_0_ Pulse width SHARED_SERDES_0_REFCLKP 0.45*tc(SHARED_ 0.55*tc(SHARED_
ns
REFCLKP) high SERDES_0_REFCLKP) SERDES_0_REFCLKP)
3 tw(SHARED_SERDES_0_ Pulse width SHARED_SERDES_0_REFCLKP 0.45*tc(SHARED_ 0.55*tc(SHARED_
ns
REFCLKP) low SERDES_0_REFCLKP) SERDES_0_REFCLKP)
4 tr(SHARED_SERDES_0_ Rise time SHARED_SERDES_0_REFCLK[P:N] 0.2*tc(SHARED_SERDES
ps
REFCLK[P:N]) differential rise time (10% to 90%) _0_REFCLK[P:N])
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