66AK2L06
SPRS930 –APRIL 2015
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Table 11-28. ARM PLL Control Register 0 Field Descriptions
Bit Field Description
31-24 BWADJ[7:0] BWADJ[11:8] and BWADJ[7:0] are located in ARMPLLCTL0 and ARMPLLCTL1 registers. BWADJ[11:0] should
be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ = ((PLLM+1)>>1) - 1.
23 BYPASS PLL bypass mode:
• 0 = PLL is not in BYPASS mode
• 1 = PLL is in BYPASS mode
22-19 CLKOD A 4-bit field that selects the values for the PLL post divider. Valid post divider values are 1 and even values
from 2 to 16. CLKOD field is loaded with output divide value minus 1
18-6 PLLM A 13-bit field that selects the values for the multiplication factor
5-0 PLLD A 6-bit field that selects the values for the reference divider
Figure 11-23. ARM PLL Control Register 1 (ARMPLLCTL1)
31 15 14 13 7 6 5 4 3 0
Reserved PLLRST Reserved ENSAT Reserved BWADJ[11:8]
RW - 00000000000000000 RW-0 RW-0000000 RW-0 R-00 RW- 0000
Legend: RW = Read/Write; -n = value after reset
Table 11-29. ARM PLL Control Register 1 Field Descriptions
Bit Field Description
31-15 Reserved Reserved
14 PLLRST PLL Reset bit
• 0 = PLL Reset is released
• 1 = PLL Reset is asserted
13-7 Reserved Reserved
6 ENSAT Needs to be set to 1 for proper PLL operation
5-4 Reserved Reserved
3-0 BWADJ[11:8] BWADJ[11:8] and BWADJ[7:0] are located in ARMPLLCTL0 and ARMPLLCTL1 registers. BWADJ[11:0] should
be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ = ((PLLM+1)>>1) - 1.
See the KeyStone Architecture Phase Locked Loop (PLL) Controller User's Guide (SPRUGV2) for the
recommended programming sequence.
11.5.6 Main PLL Controller/ARM/DFE/PCIe/USB Clock Input Electrical Data/Timing
Table 11-30. Main PLL Controller/ARM/DFE/PCIe/Shared SerDes/USB/TSREF Clock Input Timing
Requirements
(1)
(see Figure 11-24 through Figure 11-27)
NO. MIN MAX UNIT
SYSCLK[P:N]
1 tc(SYSCLKN)
(2)
Cycle time SYSCLKN cycle time 3.25 or 6.51 or 8.138 ns
1 tc(SYSCLKP)
(2)
Cycle time SYSCLKP cycle time 3.25 or 6.51 or 8.138 ns
3 tw(SYSCLKN) Pulse width SYSCLKN high 0.45*tc 0.55*tc ns
2 tw(SYSCLKN) Pulse width SYSCLKN low 0.45*tc 0.55*tc ns
2 tw(SYSCLKP) Pulse width SYSCLKP high 0.45*tc 0.55*tc ns
3 tw(SYSCLKP) Pulse width SYSCLKP low 0.45*tc 0.55*tc ns
4 tr(SYSCLK_200 mV) Transition time SYSCLK differential rise time
50 350 ps
(200 mV)
4 tf(SYSCLK_200 mV) Transition time SYSCLK differential fall time
50 350 ps
(200 mV)
5 tj(SYSCLKN) Jitter, peak_to_peak _ periodic SYSCLKN 0.2*tc(SYSCLKN) ps
5 tj(SYSCLKP) Jitter, peak_to_peak _ periodic SYSCLKP 0.2*tc(SYSCLKP) ps
(1) See the Hardware Design Guide for KeyStone II Devices application report (SPRABV0) for detailed recommendations.
(2) When DFE is used, Cycle time SYSCLKP|N min is 8.138ns
246 66AK2L06 Peripheral Information and Electrical Specifications Copyright © 2015, Texas Instruments Incorporated
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