66AK2L06
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SPRS930 –APRIL 2015
Figure 11-16. Reset Configuration Register (RSTCFG)
31 14 13 12 11 4 3 0
Reserved PLLCTLRSTTYPE RESET TYPE Reserved WDTYPE[N
(1)
]
R-0x000000 R/W-0
(2)
R/W-0
(2)
R-0x0 R/W-0x00
(2)
Legend: R = Read only; R/W = Read/Write; -n = value after reset
(1) Where N = 1, 2, 3,....N (Not all these outputs may be used on a specific device.)
(2) Writes are conditional based on valid key. For details, see Section 11.5.3.7.
Table 11-23. Reset Configuration Register Field Descriptions
Bit Field Description
31-14 Reserved Reserved
13 PLLCTLRSTTY PLL controller initiates a software-driven reset of type:
PE
• 0 = Hard reset (default)
• 1 = Soft reset
12 RESET TYPE RESET initiates a reset of type:
• 0 = Hard reset (default)
• 1 = Soft reset
11-4 Reserved Reserved
3 WDTYPE3 Watchdog timer [N] initiates a reset of type:
• 0 = Hard reset (default)
2 WDTYPE2
• 1 = Soft reset
1 WDTYPE1
0 WDTYPE0
11.5.3.9 Reset Isolation Register (RSISO)
This register is used to select the module clocks that must maintain their clocking without pausing through
non-power-on reset. Setting any of these bits effectively blocks reset to all Main PLL Control Registers in
order to maintain current values of PLL multiplier, divide ratios, and other settings. Along with setting the
module-specific bit in RSISO, the corresponding MDCTLx[12] bit also needs to be set in the PSC to reset-
isolate a particular module. For more information on the MDCTLx Register, see the KeyStone Architecture
Power Sleep Controller (PSC) User's Guide (SPRUGV4). The Reset Isolation Register (RSISO) is shown
in Figure 11-17 and described in Table 11-24.
Figure 11-17. Reset Isolation Register (RSISO)
31 9 8 7 0
Reserved SRISO Reserved
R-0 R/W-0 R-0x0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Table 11-24. Reset Isolation Register Field Descriptions
Bit Field Description
31-9 Reserved Reserved.
8 SRISO Isolate SmartReflex control
• 0 = Not reset isolated
• 1 = Reset isolated
7-0 Reserved Reserved
11.5.3.10 SerDes Reset Isolation Register (RSTISOCTL)
This register is used to control the SerDes reset isolation for AIL and SGMII lanes.
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