66AK2L06
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SPRS930 –APRIL 2015
11.5.3.4 PLLDIV Divider Ratio Change Status Register (DCHANGE)
Whenever a different ratio is written to the PLLDIV n registers, the PLL CTL flags the change in the
DCHANGE Status Register. During the GO operation, the PLL controller changes only the divide ratio of
the SYSCLKs with the bit set in DCHANGE. Note that the ALNCTL Register determines if that clock also
needs to be aligned to other clocks. The PLLDIV Divider Ratio Change Status Register is shown in
Figure 11-12 and described in Table 11-19.
Figure 11-12. PLLDIV Divider Ratio Change Status Register (DCHANGE)
31 5 4 3 2 0
Reserved SYS4 SYS3 Reserved
R-0 R/W-1 R/W-1 R-0
Legend: R/W = Read/Write; R = Read only; -n = value after reset, for reset value
Table 11-19. PLLDIV Divider Ratio Change Status Register Field Descriptions
Bit Field Description
31-5
Reserved Reserved. This bit location is always read as 0. A value written to this field has no effect.
2-0
4 SYS4 Identifies when the SYSCLK n divide ratio has been modified.
3 SYS3
• 0 = SYSCLK n ratio has not been modified. When GOSET is set, SYSCLK n will not be affected.
• 1 = SYSCLK n ratio has been modified. When GOSET is set, SYSCLK n will change to the new ratio.
11.5.3.5 SYSCLK Status Register (SYSTAT)
The SYSCLK Status Register (SYSTAT) shows the status of SYSCLK[4:1]. SYSTAT is shown in
Figure 11-13 and described in Table 11-20.
Figure 11-13. SYSCLK Status Register (SYSTAT)
31 4 3 2 1 0
Reserved SYS4ON SYS3ON SYS2ON SYS1ON
R-n R-1 R-1 R-1 R-1
Legend: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-20. SYSCLK Status Register Field Descriptions
Bit Field Description
31-4 Reserved Reserved. This location is always read as 0. A value written to this field has no effect.
3-0 SYS[N
(1)
]ON SYSCLK[N] on status
• 0 = SYSCLK[N] is gated
• 1 = SYSCLK[N] is on
(1) Where N = 1, 2, 3, or 4
11.5.3.6 Reset Type Status Register (RSTYPE)
The Reset Type Status (RSTYPE) Register latches the cause of the last reset. If multiple reset sources
occur simultaneously, this register latches the highest priority reset source. The Reset Type Status
Register is shown in Figure 11-14 and described in Table 11-21.
Figure 11-14. Reset Type Status Register (RSTYPE)
31 29 28 27 12 11 8 7 3 2 1 0
Reserved EMU-RST Reserved WDRST[N] Reserved PLLCTRLRST RESET POR
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
Legend: R = Read only; -n = value after reset
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