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66AK2L06

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型号: 66AK2L06
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功能描述: 66AK2L06 Multicore DSPARM KeyStone II System-on-Chip (SoC)
PDF文件大小: 1516.59 Kbytes
PDF页数: 共298页
制造商: TI[Texas Instruments]
制造商LOGO: TI[Texas Instruments] LOGO
制造商网址: http://www.ti.com
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120%
66AK2L06
www.ti.com
SPRS930 APRIL 2015
Table 11-15. PLL Controller Registers (Including Reset Controller) (continued)
HEX ADDRESS RANGE ACRONYM REGISTER NAME
00 0231 010C - Reserved
00 0231 0110 PLLM PLL Multiplier Control Register
00 0231 0114 - Reserved
00 0231 0118 PLLDIV1 PLL Controller Divider 1Register
00 0231 011C PLLDIV2 PLL Controller Divider 2 Register
00 0231 0120 PLLDIV3 PLL Controller Divider 3Register
00 0231 0124 - Reserved
00 0231 0128 POSTDIV PLL Controller Post-Divide Register
00 0231 012C - 00 0231 0134 - Reserved
00 0231 0138 PLLCMD PLL Controller Command Register
00 0231 013C PLLSTAT PLL Controller Status Register
00 0231 0140 ALNCTL PLL Controller Clock Align Control Register
00 0231 0144 DCHANGE PLLDIV Ratio Change Status Register
00 0231 0148 CKEN Reserved
00 0231 014C CKSTAT Reserved
00 0231 0150 SYSTAT SYSCLK Status Register
00 0231 0154 - 00 0231 015C - Reserved
00 0231 0160 PLLDIV4 PLL Controller Divider 4Register
00 0231 0164 PLLDIV5 Reserved
00 0231 0168 PLLDIV6 Reserved
00 0231 016C PLLDIV7 Reserved
00 0231 0170 PLLDIV8 Reserved
00 0231 0174 - 00 0231 0193 PLLDIV9 - PLLDIV16 Reserved
00 0231 0194 - 00 0231 01FF - Reserved
11.5.3.1 PLL Secondary Control Register (SECCTL)
The PLL Secondary Control Register contains extra fields to control the Main PLL and is shown in
Figure 11-9 and described in Table 11-16.
Figure 11-9. PLL Secondary Control Register (SECCTL)
31 24 23 22 19 18 0
Reserved BYPASS OUTPUT DIVIDE Reserved
R-0000 0000 RW-1 RW-0001 RW-001 0000 0000 0000 0000
Legend: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-16. PLL Secondary Control Register Field Descriptions
Bit Field Description
31-24 Reserved Reserved
23 BYPASS PLL bypass mode:
0 = PLL is not in BYPASS mode
1 = PLL is in BYPASS mode
22-19 OUTPUT DIVIDE Output divider ratio bits
0h = ÷1. Divide frequency by 1
1h = ÷2. Divide frequency by 2
2h = ÷3. Divide frequency by 3
3h = ÷4. Divide frequency by 4
4h - Fh = ÷5 to ÷16. Divide frequency range: divide frequency by 5 to divide frequency by 80.
18-0 Reserved Reserved
Copyright © 2015, Texas Instruments Incorporated 66AK2L06 Peripheral Information and Electrical Specifications 239
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