66AK2L06
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SPRS930 –APRIL 2015
Table 11-13. Main PLL Controller Module Clock Domains Internal and Shared Local Clock Dividers
INTERNAL CLOCK SHARED LOCAL CLOCK
CLOCK MODULE DIVIDER(S) DIVIDER
SYSCLK1 Internal Clock Dividers
ARM CorePac /1, /3, /6, --
Reserved
C66x DSP CorePacs /1, /2, /3, /4 --
Chip Interrupt Controllers (CICx) /6 --
DFE /3
IQN /3, /6
DDR3 Memory Controller A (also receives clocks from the /2 --
DDR3A_PLL)
EMIF16 /6 --
Reserved
Fast Fourier Transform Coprocessor (FFTC) /3 --
SYSCLK1
Multicore Navigator Queue Manager /3 --
MultiCore Shared Memory Controller (MSMC) /1 --
PCI express (PCIe) /2, /3, /4, /6 --
Reserved
ROM /6 --
Serial Gigabit Media Independent Interface (SGMII) /2, /3, /6, /8 --
Reserved
Reserved
Universal Asynchronous Receiver/Transmitter (UART) /6 --
Universal Serial Bus 3.0 (USB 3.0) /3, /6 --
SYSCLK1 Shared Local Clock Dividers
Power/Sleep Controller (PSC) -- /12, /24
EDMA
SYSCLK1 Memory Protection Units (MPUx)
-- /3
Semaphore
TeraNet (SYSCLK1/3 domain)
DFE
CSISC2_0
CSISC2_1
Boot Config
General-Purpose Input/Output (GPIO)
SYSCLK1 -- /6
I
2
C
Security Manager
Serial Peripheral Interconnect (SPI)
TeraNet (CPU /6 domain)
Timers
SYSCLK2 Internal Clock Dividers
SYSCLK2 SmartReflex /12, /128 --
11.5.2.3 Module Clock Input
Table 11-7 lists various clock domains in the device and their distribution in each peripheral. The table
also shows the distributed clock division in modules and their mapping with source clocks of the device
PLLs.
Copyright © 2015, Texas Instruments Incorporated 66AK2L06 Peripheral Information and Electrical Specifications 237
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