66AK2L06
SPRS930 –APRIL 2015
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11.5.2 Main PLL Controller Device-Specific Information
11.5.2.1 Internal Clocks and Maximum Operating Frequencies
The Main PLL, used to drive the C66x CorePacs, the switch fabric, and a majority of the peripheral clocks
(all but the ARM CorePacs, DDR3 and the NETCP modules) requires a PLL Controller to manage the
various clock divisions, gating, and synchronization. Unlike other PLL, CLKOD functionality of Main PLL is
replaced by PLL controller Post-Divider register (POSTDIV). The POSTDIV.RATIO[3:0] and
POSTDIV.POSTDEN bits control the post divider ratio and divider enable respectively. PLLM[5:0] input of
the Main PLL is controlled by the PLL controller PLLM register.
The Main PLL Controller has four SYSCLK outputs that are listed below, along with the clock descriptions.
Each SYSCLK has a corresponding divider that divides down the output clock of the PLL. Note that
dividers are not programmable unless explicitly mentioned in the description below.
• SYSCLK1: Full-rate clock for all C66x CorePacs. Using local dividers, SYSCLK1 is used to derive
clocks required for the majority of peripherals that do not need reset isolation.
The system peripherals and modules driven by SYSCLK1 are as follows; however, not all peripherals
are supported in every part. See Section 1 for the complete list of peripherals supported in your part:
DFE, FFTC, IQN, EMIF16, USB 3.0, USIM, PCIe, SGMII, GPIO, Timer64, I
2
C, SPI, TeraNet, UART,
ROM, CIC, Security Manager, BootCFG, PSC, Queue Manager, Semaphore, MPUs, EDMA, MSMC,
DDR3 EMIF.
• SYSCLK2: Full-rate, reset-isolated clock used to generate various other clocks required by peripherals
that need reset isolation: e.g., SmartReflex.
• SYSCLK3: 1/x-rate clock used to clock the C66x CorePac emulation. The default rate for this clock is
1/3. This clock is programmable from /1 to /32, where this clock does not violate the maximum of 350
MHz. SYSCLK3 can be turned off by software.
• SYSCLK4: 1/z-rate clock for the system trace module only. The default rate for this clock is 1/5. This
clock is configurable: the maximum configurable clock is 210 MHz and the minimum configuration
clock is 32 MHz. SYSCLK4 can be turned off by software.
Only SYSCLK3 and SYSCLK4 are programmable.
11.5.2.2 Local Clock Dividers
The clock signals from the Main PLL Controller are routed to various modules and peripherals on the
device. Some modules and peripherals have one or more internal clock dividers. Other modules and
peripherals have no internal clock dividers, but are grouped together and receive clock signals from a
shared local clock divider. Internal and shared local clock dividers have fixed division ratios (see Table 11-
13).
236 66AK2L06 Peripheral Information and Electrical Specifications Copyright © 2015, Texas Instruments Incorporated
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