MAIN PLLOUT
SYSCLK(N|P)
ALTCORECLK(N|P)
DDR3CLK
PLLD
VCO
PLLM
Main PLL
CLKOD
BYPASS
0
1
CORECLKSEL[1:0]
SYSCLK4
/z
PLLDIV4
SYSCLK3
/x
PLLDIV3
SYSCLK2
/1
PLLDIV2
To Switch Fabric,
Accelerators,
SmartReflex, etc.
PLL Controller
SYSCLK1
/1
PLLDIV1
POSTDIV
Peripherals, etc.
C66x
CorePacs
SYSCLK1
66AK2L06
www.ti.com
SPRS930 –APRIL 2015
Figure 11-8. Main PLL and PLL Controller
Note that the Main PLL Controller registers can be accessed by any master in the device. The PLLM[5:0]
bits of the multiplier are controlled by the PLLM Register inside the PLL Controller and the PLLM[12:6] bits
are controlled by the chip-level MAINPLLCTL0 Register. The output divide and bypass logic of the PLL
are controlled by fields in the SECCTL Register in the PLL Controller. Only PLLDIV3, and PLLDIV4 are
programmable on the device. See the KeyStone Architecture Phase Locked Loop (PLL) Controller User's
Guide (SPRUGV2) for more details on how to program the PLL controller.
The multiplication and division ratios within the PLL and the post-division for each of the chip-level clocks
are determined by a combination of this PLL and the Main PLL Controller. The Main PLL Controller also
controls reset propagation through the chip, clock alignment, and test points. The Main PLL Controller
monitors the PLL status and provides an output signal indicating when the PLL is locked.
Main PLL power is supplied externally via the Main PLL power-supply pin (AVDDA1). An external EMI
filter circuit must be added to all PLL supplies. See the Hardware Design Guide for KeyStone II Devices
application report (SPRABV0) for detailed recommendations. For the best performance, TI recommends
that all the PLL external components be on a single side of the board without jumpers, switches, or
components other than those shown. For reduced PLL jitter, maximize the spacing between switching
signal traces and the PLL external components (C1, C2, and the EMI Filter).
The minimum SYSCLK rise and fall times should also be observed. For the input clock timing
requirements, see Section 11.5.6.
It should be assumed that any registers not included in these sections are not supported by the device.
Furthermore, only the bits within the registers described here are supported. Avoid writing to any reserved
memory location or changing the value of reserved bits.
The PLL Controller module as described in the KeyStone Architecture Phase Locked Loop (PLL)
Controller User's Guide (SPRUGV2) includes a superset of features, some of which are not supported on
the 66AK2L06 device. The following sections describe the registers that are supported.
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