66AK2L06
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SPRS930 –APRIL 2015
Table 11-7. Clock Domains (continued)
LPSC NUMBER MODULE(S) NOTES
47 Reserved
48 Reserved
49 Reserved
50 Reserved
50 IQN_AIL Software control
51 ARM Smart Reflex Software control
52 ARM CorePac Software control
No LPSC Bootcfg, PSC, and PLL Controller These modules do not use LPSC
11.3.3 PSC Register Memory Map
Table 11-8 shows the PSC Register memory map.
Table 11-8. PSC Register Memory Map
OFFSET REGISTER DESCRIPTION
0x000 PID Peripheral Identification Register
0x004 - 0x010 Reserved Reserved
0x014 VCNTLID Voltage Control Identification Register
0x018 - 0x11C Reserved Reserved
0x120 PTCMD Power Domain Transition Command Register
0x124 Reserved Reserved
0x128 PTSTAT Power Domain Transition Status Register
0x12C - 0x1FC Reserved Reserved
0x200 PDSTAT0 Power Domain Status Register 0
0x204 PDSTAT1 Power Domain Status Register 1
0x208 PDSTAT2 Power Domain Status Register 2
0x20C PDSTAT3 Power Domain Status Register 3
0x210 PDSTAT4 Power Domain Status Register 4
0x214 PDSTAT5 Power Domain Status Register 5
0x218 PDSTAT6 Power Domain Status Register 6
0x21C PDSTAT7 Power Domain Status Register 7
0x220 PDSTAT8 Power Domain Status Register 8
0x224 PDSTAT9 Power Domain Status Register 9
0x228 PDSTAT10 Power Domain Status Register 10
0x22C PDSTAT11 Power Domain Status Register 11
0x230 PDSTAT12 Power Domain Status Register 12
0x234 PDSTAT13 Power Domain Status Register 13
0x238 PDSTAT14 Power Domain Status Register 14
0x23C PDSTAT15 Power Domain Status Register 15
0x240 PDSTAT16 Power Domain Status Register 16
0x244 PDSTAT17 Power Domain Status Register 17
0x248 PDSTAT18 Power Domain Status Register 18
0x24C PDSTAT19 Power Domain Status Register 19
0x250 PDSTAT20 Power Domain Status Register 20
0x254 PDSTAT21 Power Domain Status Register 21
0x258 PDSTAT22 Power Domain Status Register 22
0x25C PDSTAT23 Power Domain Status Register 23
0x260 PDSTAT24 Power Domain Status Register 24
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