66AK2L06
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SPRS930 –APRIL 2015
11.3.1 Power Domains
The device has several power domains that can be turned on for operation or off to minimize power
dissipation. The Global Power Sleep Controller (GPSC) is used to control the power gating of various
power domains.
The following table shows the 66AK2L06 power domains.
Table 11-6. Power Domains
DOMAIN BLOCK(S) NOTE POWER CONNECTION
0 Most peripheral logic (BOOTCFG, Cannot be disabled Always on
EMIF16, I
2
C, INTC, GPIO, USB,
USIM)
1 Per-core TETB and system TETB RAMs can be powered down Software control
2 Network Coprocessor Logic can be powered down Software control
3 PCIe0 Logic can be powered down Software control
4 PCIe1 Logic can be powered down Software control
5 DFE__PD2 Logic can be powered down Software control
6 Smart Reflex
7 MSMC RAM MSMC RAM can be powered down Software control
8 C66x Core 0, L1/L2 RAMs L2 RAMs can sleep
Software control via C66x CorePac. For
9 C66x Core 1, L1/L2 RAMs L2 RAMs can sleep
details, see the TMS320C66x DSP CorePac
10 C66x Core 2, L1/L2 RAMs L2 RAMs can sleep
User's Guide (SPRUGW0).
11 C66x Core 3, L1/L2 RAMs L2 RAMs can sleep
12 Reserved
13 Reserved
14 Reserved
15 Reserved
16 EMIF(DDR3A) Logic can be powered down Software control
17 Reserved
18 DFE_PD0 Logic can be powered down Software control
19 FFTC_0 Logic can be powered down Software control
20 Reserved
21 OSR (On Chip Standalone RAM) RAMs can be powered down Software control
22 Reserved
23 Reserved
24 Reserved
25 Reserved
26 Reserved
27 DFE_PD1 Logic can be powered down Software control
28 FFTC_1 Logic can be powered down Software control
29 IQN_AIL Logic can be powered down Software control
30 Reserved
31 ARM CorePac Logic can be powered down Software control
11.3.2 Clock Domains
Clock gating to each logic block is managed by the Local Power Sleep Controllers (LPSCs) of each
module. For modules with a dedicated clock or multiple clocks, the LPSC communicates with the PLL
controller to enable and disable that module's clock(s) at the source. For modules that share a clock with
other modules, the LPSC controls the clock gating logic for each module.
Table 11-7 shows the 66AK2L06 clock domains.
Copyright © 2015, Texas Instruments Incorporated 66AK2L06 Peripheral Information and Electrical Specifications 223
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