VCNTL[4:2]
VCNTL[5]
1
2
4
LSB VID[2:0] MSB VID[5:3]
3
66AK2L06
SPRS930 –APRIL 2015
www.ti.com
11.2.4 SmartReflex
Increasing the device complexity increases its power consumption. With higher clock rates and increased
performance comes an inevitable penalty: increasing leakage currents. Leakage currents are present in
any powered circuit, independent of clock rates and usage scenarios. This static power consumption is
mainly determined by transistor type and process technology. Higher clock rates also increase dynamic
power, which is the power used when transistors switch. The dynamic power depends mainly on a specific
usage scenario, clock rates, and I/O activity.
Texas Instruments SmartReflex technology is used to decrease both static and dynamic power
consumption while maintaining the device performance. SmartReflex in the 66AK2L06 device is a feature
that allows the core voltage to be optimized based on the process corner of the device. This requires a
voltage regulator for each 66AK2L06 device.
The 66AK2L06 device supports SmartReflex Class0 and 'Class0 with Temperature Compensation'. To
help maximize performance and minimize power consumption of the device, SmartReflex 'Class0 with
Temperature Compensation' needs to be implemented. Power consumption is expected to be higher with
only Class0 as compared to 'Class0 with Temperature Compensation'. The voltage selection can be
accomplished using 4 VCNTL pins or 6 VCNTL pins (depending on power supply device being used),
which are used to select the output voltage of the core voltage regulator.
For information on implementation of SmartReflex see the Power Consumption Summary for KeyStone
TCI66x Devices application report (SPRABL4) and the Hardware Design Guide for KeyStone II Devices
application report (SPRABV0).
Table 11-5. SmartReflex 4-Pin 6-bit VID Interface Switching Characteristics
(see Figure 11-3)
NO. PARAMETER MIN MAX UNIT
1 td(VCNTL[4:2]-VCNTL[5]) Delay time - VCNTL[4:2] valid after VCNTL[5] low 300.00 ns
2 toh(VCNTL[5]-VCNTL[4:2]) Output hold time - VCNTL[4:2] valid after VCNTL[5] 0.07 172020C
(1)
ms
3 td(VCNTL[4:2]-VCNTL[5]) Delay time - VCNTL[4:2] valid after VCNTL[5] high 300.00 ns
4 toh(VCNTL[5]-VCNTL[2:0) Output hold time - VCNTL[4:2] valid after VCNTL[5] high 0.07 172020C ms
(1) C = 1/SYSCLK1 frequency, in ms (see Figure 11-10)
Figure 11-3. SmartReflex 4-Pin 6-Bit VID Interface Timing
11.3 Power Sleep Controller (PSC)
The Power Sleep Controller (PSC) includes a Global Power Sleep Controller (GPSC) and a number of
Local Power Sleep Controllers (LPSC) that control overall device power by turning off unused power
domains and gating off clocks to individual peripherals and modules. The PSC provides the user with an
interface to control several important power and clock operations.
For information on the Power Sleep Controller, see the KeyStone Architecture Power Sleep Controller
(PSC) User's Guide (SPRUGV4).
222 66AK2L06 Peripheral Information and Electrical Specifications Copyright © 2015, Texas Instruments Incorporated
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