RESET
RESETFULL
POR
CVDD
CVDD1
DVDDR
USBxDVDD33
SYSCLK1
DDRCLKOUT
RESETSTAT
Power Stabilization Phase Device Initialization Phase
3a
2a
2d
Configuration
Inputs
9
8
11
1
VDDALV
USBxVP
USBxVPTX
2b
VDDAHV
AVDDAx
DVDD18
3
7
2c
10
1
2
3
4
5
6
4
5
66AK2L06
SPRS930 –APRIL 2015
www.ti.com
Figure 11-1. Core-Before-IO Power Sequencing
218 66AK2L06 Peripheral Information and Electrical Specifications Copyright © 2015, Texas Instruments Incorporated
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