66AK2L06
SPRS930 –APRIL 2015
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Table 9-70. USB_PHY_CTL5 Register Field Descriptions
Bit Field Description
31-21 Reserved Reserved
20 PHY_REF_CLKDIV2 Input Reference Clock Divider Control.
If the input reference clock frequency is greater than 100 MHz, this signal must be asserted.
The reference clock frequency is then divided by 2 to keep it in the range required by the
MPLL.
When this input is asserted, the ref_ana_usb2_clk (if used) frequency will be the reference
clock frequency divided by 4.
19-13 PHY_MPLL_MULTIPLIER[6:0] MPLL Frequency Multiplier Control.
Multiplies the reference clock to a frequency suitable for intended operating speed.
12-4 PHY_SSC_REF_CLK_SEL Spread Spectrum Reference Clock Shifting.
Enables non-standard oscillator frequencies to generate targeted MPLL output rates. Input
corresponds to frequency-synthesis coefficient.
• . ssc_ref_clk_sel[8:6] = modulous - 1
• . ssc_ref_clk_sel[5:0] = 2's complement push amount.
3 Reserved Reserved
2-0 PHY_SSC_RANGE Spread Spectrum Clock Range.
Selects the range of spread spectrum modulation when ssc_en is asserted and the PHY is
spreading the high-speed transmit clocks. Applies a fixed offset to the phase accumulator.
210 Device Boot and Configuration Copyright © 2015, Texas Instruments Incorporated
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