66AK2L06
SPRS930 –APRIL 2015
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Table 9-66. USB_PHY_CTL1 Register Field Descriptions (continued)
Bit Field Description
2 PIPE_ALT_CLK_SEL Alternate Clock Source Select.
Selects the alternate clock sources instead of the internal MPLL outputs for the PCS clocks.
• 1 = Uses alternate clocks.
• 0 = Users internal MPLL clocks.
Change only during a reset.
1 PIPE_ALT_CLK_REQ Alternate Clock Source Request.
Indicates that the alternate clocks are needed by the slave PCS (that is, to boot the master
MPLL). Connect to the alt_clk_en on the master.
0 PIPE_ALT_CLK_EN Alternate Clock Enable.
Enables the ref_pcs_clk and ref_pipe_pclk output clocks (if necessary, powers up the MPLL).
Figure 9-52. USB_PHY_CTL2 Register
31 30 29 27 26 23 22 21
Reserved PHY_PC_LOS_BIAS PHY_PC_TXVREFTUNE PHY_PC_TXRISETUNE
R-0 R/W-101 R/W-1000 R/W-01
20 19 18 17 16 15 14
PHY_PC_TXRESTUNE PHY_PC_ PHY_PC_TXPREEMPAMPTUNE PHY_PC_
TXPREEMPPULSETUNE TXHSXVTUNE
R/W-01 R/W-0 R/W-00 R/W-11
13 10 9 7 6 4 3 2 0
PHY_PC_TXFSLSTUNE PHY_PC_SQRXTUNE PHY_PC_OTGTUNE Reserved PHY_PC_
COMPDISTUNE
R/W-0011 R/W-011 R/W-100 R-0 R/W-100
Legend: R = Read only; R/W = Read/Write, -n = value after reset
Table 9-67. USB_PHY_CTL2 Register Field Descriptions
Bit Field Description
31-30 Reserved Reserved
29-27 PHY_PC_LOS_BIAS Loss-of-Signal Detector Threshold Level Control.
Sets the LOS detection threshold level.
• +1 = results in a +15 mVp incremental change in the LOS threshold.
• -1 = results in a -15 mVp incremental change in the LOS threshold.
Note: the 000b setting is reserved and must not be used.
26-23 PHY_PC_TXVREFTUNE HS DC Voltage Level Adjustment.
Adjusts the high-speed DC level voltage.
• +1 = results in a +1.25% incremental change in high-speed DC voltage level.
• -1 = results in a -1.25% incremental change in high-speed DC voltage level.
22-21 PHY_PC_TXRISETUNE HS Transmitter Rise/Fall TIme Adjustment.
Adjusts the rise/fall times of the high-speed waveform.
• +1 = results in a -4% incremental change in the HS rise/fall time.
• -1 = results in a +4% incremental change in the HS rise/fall time.
20-19 PHY_PC_TXRESTUNE USB Source Impedance Adjustment.
Some applications require additional devices to be added on the USB, such as a series
switch, which can add significant series resistance. This bus adjusts the driver source
impedance to compensate for added series resistance on the USB.
206 Device Boot and Configuration Copyright © 2015, Texas Instruments Incorporated
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