66AK2L06
SPRS930 –APRIL 2015
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Table 9-58. ARM Endian Configuration Register 2
Default Values
DEFAULT
ARM ENDIAN CONFIGURATION REGISTER 2 VALUES
ARMENDIAN_CFG0_2 0x00000001
ARMENDIAN_CFG1_2 0x00000001
ARMENDIAN_CFG2_2 0x00000001
ARMENDIAN_CFG3_2 0x00000001
ARMENDIAN_CFG4_2 0x00000001
ARMENDIAN_CFG5_2 0x00000001
ARMENDIAN_CFG6_2 0x00000001
ARMENDIAN_CFG7_2 0x00000001
Table 9-59. ARM Endian Configuration Register 2 Field Descriptions
Bit Field Description
31-1 Reserved Reserved
0 DIS Disabling the word swap of a region
• 0 : Enable word swap for region
• 1 : Disable word swap for region
9.2.3.28 Chip Miscellaneous Control (CHIP_MISC_CTL0) Register
Figure 9-45. Chip Miscellaneous Control Register (CHIP_MISC_CTL0)
31 19 18 17
Reserved USB_PME_EN Reserved
R-0 RW-0 R-0
16 13 12 11 3 2 0
Reserved MSMC_BLOCK_PARITY_RST Reserved QM_PRIORITY
R-0 RW-0 RW-0 RW-0
Legend: R = Read only; W = Write only; -n = value after reset
Table 9-60. Chip Miscellaneous Control Register (CHIP_MISC_CTL0) Field Descriptions
Bit Field Description
31-19 Reserved Reserved.
18 USB_PME_EN Enables wakeup event generation from USB
• 0 = Disable PME event generation
• 1 = Enable PME event generation
17-13 Reserved
12 MSMC_BLOCK_PARITY_RST Controls MSMC parity RAM reset. When set to ‘1’ means the MSMC parity RAM will not be reset.
11-3 Reserved Reserved
2-0 QM_PRIORITY Control the priority level for the transactions from QM_Master port, which access the external
linking RAM.
9.2.3.29 Chip Miscellaneous Control (CHIP_MISC_CTL1) Register
Figure 9-46. Chip Miscellaneous Control Register (CHIP_MISC_CTL1)
31 12 11 10 0
Reserved DDR3A_PSC_LOCK_n Reserved
R- 0 RW-0 RW-0000000000000
Legend: R = Read only; RW = Read/Write; -n = value after reset
202 Device Boot and Configuration Copyright © 2015, Texas Instruments Incorporated
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