66AK2L06
SPRS930 –APRIL 2015
www.ti.com
1.2 Applications
• Medical • Avionics and Defense
• Test and Measurement • Industrial
1.3 KeyStone Architecture
TI’s KeyStone Multicore Architecture provides a high-performance structure for integrating RISC and DSP
cores with application-specific coprocessors and I/O. KeyStone is the first of its kind in that it provides
adequate internal bandwidth for non-blocking access to all processing cores, peripherals, coprocessors,
and I/O. This is achieved with four main hardware elements: Multicore Navigator, TeraNet, and Multicore
Shared Memory Controller.
Multicore Navigator is an innovative packet-based manager that controls 8K queues. When tasks are
allocated to the queues, Multicore Navigator provides hardware-accelerated dispatch that directs tasks to
the appropriate available hardware. The packet-based system on a chip (SoC) uses the 2-Tbps capacity
of the TeraNet switched central resource to move packets. The Multicore Shared Memory Controller
enables processing cores to access shared memory directly without drawing from the TeraNet’s capacity,
so packet movement cannot be blocked by memory access.
1.4 Device Description
The 66AK2L06 KeyStone SoC is a member of the C66x family based on TI's new KeyStone II Multicore
SoC Architecture and is a low-power solution with integrated JESD204B lanes that meets the more
stringent power, size, and cost requirements of applications requiring connectivity with ADC and DAC
based applications. The device’s ARM and DSP cores deliver exceptional processing power on platforms
requiring high signal and control processing.
TI's KeyStone II Architecture provides a programmable platform integrating various subsystems (ARM
CorePac, C66x CorePacs, IP network, Digital Front End, and FFT processing) and uses a queue-based
communication system that allows the SoC resources to operate efficiently and seamlessly. This unique
SoC architecture also includes a TeraNet switch that enables the wide mix of system elements, from
programmable cores to dedicated coprocessors and high-speed IO, to each operate at maximum
efficiency with no blocking or stalling.
The addition of the ARM CorePac in the 66AK2L06 device enables the ability for complex control code
processing on-chip. Operations such as housekeeping and management processing can be performed
with the Cortex-A15 processor.
TI's new C66x core launches a new era of DSP technology by combining fixed-point and floating-point
computational capability in the processor without sacrificing speed, size, or power consumption. The raw
computational performance is an industry-leading 38.4 GMACS/core and 19.2 Gflops/core (@ 1.2 GHz
operating frequency). The C66x is also 100% backward compatible with software for C64x+ devices. The
C66x CorePac incorporates 90 new instructions targeted for floating point (FPi) and vector math oriented
(VPi) processing.
The 66AK2L06 contains many coprocessors to offload the bulk of the processing demands of higher
layers of application. This keeps the cores free for algorithms and other differentiating functions. The SoC
contains multiple copies of key coprocessors such as the FFTC. The architectural elements of the SoC
(Multicore Navigator) ensure that data is processed without any CPU intervention or overhead, allowing
the system to make optimal use of its resources.
TI's scalable multicore SoC architecture solutions provide developers with a range of software-compatible
and hardware-compatible devices to minimize development time and maximize reuse.
The 66AK2L06 device has a complete set of development tools that includes: a C compiler, an assembly
optimizer to simplify programming and scheduling, and a Windows and Linux debugger interface for
visibility into source code execution.
2 66AK2L06 Features and Description Copyright © 2015, Texas Instruments Incorporated
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