66AK2L06
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SPRS930 –APRIL 2015
Table 9-51. Device Speed Register Field Descriptions (continued)
Bit Field Description
11-0 ARMSPEED Indicates the speed of the ARM (read only)
• 0b0000 0000 0000 = 800 MHz
• 0b0000 0000 0001 = 1000 MHz
• 0b0000 0000 001x = 1200 MHz
• 0b0000 0000 01xx = Reserved
• 0b0000 0000 1xxx = Reserved
• 0b0000 0001 xxxx = Reserved
• 0b0000 001x xxxx = Reserved
• 0b0000 01xx xxxx = Reserved
• 0b0000 1xxx xxxx = 1200 MHz
• 0b0001 xxxx xxxx= 1000 MHz
• 0b001x xxxx xxxx = 800 MHz
9.2.3.23 IQN Reset Request Control (IQN_RSTREQ_CTL) Register
Incoming CPRI packet via IQN-AIL lanes can request for a device reset. This reset request is controlled
and the status is latched by the IQN_RSTREQ_CTL register.The register is shown below.
Figure 9-40. IQN Reset Request Control Register (IQN_RSTREQ_CTL)
31 10 9 8 5 4 3 2 1 0
Reserved EVTSTATCLR Reserved EVTSTAT Reserved EN Reserved
R-0 RC-0 R-0 R-0 R-0 RW-0 R-0
Legend: R = Read only; -n = value after reset
Table 9-52. IQN Reset Request Control Register Field Descriptions
Bit Field Description
31-10 Reserved Reserved. Read only
9 EVTSTATCLR Event status clear
• 0 = writing 0 to this bit has not effect
• 1= writing 1 to this bit clears EVTSTAT
8-5 Reserved Reserved. Read only
4 EVTSTAT Event status. This bit is cleared only on POR and RESETFULL .
• 0 = No IQN reset event occurred.
• 1= IQN reset received by SoC. This bit is set only when the request is enabled by setting the EN bit to 1.
3-2 Reserved Reserved. Read only
1 EN IQN reset request enable.
• 0 = IQN reset request is masked (disabled).
• 1= IQN reset request is enabled. The reset signal from IQN causes device reset signal to the PLL controller.
0 Reserved Reserved. Read only
9.2.3.24 SerDes Reset Isolation (RSTISOCTL) Register
This register is used to control the SerDes reset isolation for AIL and SGMII lanes. When AILRSTISOEN
bit is set to ‘1’, it indicates that the AIL serdes lanes must not be reset during Non-POR chip resets. When
SGMIIRSTISOEN bit is set to ‘1’, it indicates that the SGMII serdes lanes must not be reset during Non-
POR chip resets.
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