66AK2L06
SPRS930 –APRIL 2015
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Table 9-50. Reset Mux Register 8 and 9 (RSTMUX8-RSTMUX9) Field Descriptions (continued)
Bit Field Description
3-1 OMODE Timer event operation mode
• 000b = WD timer event input to the Reset Mux block does not cause any output event (default)
• 001b = Reserved
• 010b = Cortex-A15 processor watchdog timers, the Local Reset output event of the RSTMUX logic
generates reset to PLL Controller.
• 011b = WD Timer Event input to the Reset Mux block causes Local Reset output event of the RSTMUX
logic to generate reset to PLL Controller.
• 100b = WD Timer Event input to the Reset Mux block causes an interrupt to be sent to the GIC.
• 101b = WD timer event input to the Reset Mux block causes device reset to 66AK2L06. Note that for
Cortex-A15 processor watchdog timers, the Local Reset output event of the RSTMUX logic is connected to
the Device Reset generation to generate reset to PLL Controller.
• 110b = Reserved
• 111b = Reserved
0 LOCK Lock register fields
• 0 = Register fields are not locked (default)
• 1 = Register fields are locked until the next timer reset
9.2.3.22 Device Speed (DEVSPEED) Register
The Device Speed Register shows the device speed grade and is shown below.
Figure 9-39. Device Speed Register (DEVSPEED)
31 28 27 16 15 12 11 0
Reserved DEVSPEED Reserved ARMSPEED
R-n R-n
Legend: R = Read only; -n = value after reset
Table 9-51. Device Speed Register Field Descriptions
Bit Field Description
31-28 Reserved Reserved. Read only
27-16 DEVSPEED Indicates the speed of the device (read only)
• 0b0000 0000 0000 = 800 MHz
• 0b0000 0000 0001 = 1000 MHz
• 0b0000 0000 001x = 1200 MHz
• 0b0000 0000 01xx = Reserved
• 0b0000 0000 1xxx = Reserved
• 0b0000 0001 xxxx = Reserved
• 0b0000 001x xxxx = Reserved
• 0b0000 01xx xxxx = Reserved
• 0b0000 1xxx xxxx = 1200 MHz
• 0b0001 xxxx xxxx= 1000 MHz
• 0b001x xxxx xxxx = 800 MHz
15-12 Reserved Reserved. Read only
198 Device Boot and Configuration Copyright © 2015, Texas Instruments Incorporated
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