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66AK2L06

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型号: 66AK2L06
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  • 66AK2L06 PDF文件
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功能描述: 66AK2L06 Multicore DSPARM KeyStone II System-on-Chip (SoC)
PDF文件大小: 1516.59 Kbytes
PDF页数: 共298页
制造商: TI[Texas Instruments]
制造商LOGO: TI[Texas Instruments] LOGO
制造商网址: http://www.ti.com
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120%
66AK2L06
www.ti.com
SPRS930 APRIL 2015
Table 9-49. Reset Mux Register 0..3 (RSTMUX0-RSTMUX3) Field Descriptions (continued)
Bit Field Description
7-5 DELAY Delay cycles between NMI & local reset
000b = 256 SYSCLK1/6 cycles delay between NMI & local reset, when OMODE = 100b
001b = 512 SYSCLK1/6 cycles delay between NMI & local reset, when OMODE = 100b
010b = 1024 SYSCLK1/6 cycles delay between NMI & local reset, when OMODE = 100b
011b = 2048 SYSCLK1/6 cycles delay between NMI & local reset, when OMODE = 100b
100b = 4096 SYSCLK1/6 cycles delay between NMI & local reset, when OMODE = 100b (default)
101b = 8192 SYSCLK1/6 cycles delay between NMI & local reset, when OMODE = 100b
110b = 16384 SYSCLK1/6 cycles delay between NMI & local reset, when OMODE = 100b
111b = 32768 SYSCLK1/6 cycles delay between NMI & local reset, when OMODE = 100b
4 EVTSTAT Event status
0 = No event received (Default)
1 = WD timer event received by Reset Mux block
3-1 OMODE Timer event operation mode
000b = WD timer event input to the Reset Mux block does not cause any output event (default)
001b = Reserved
010b = WD Timer Event input to the Reset Mux block causes local reset input to C66x CorePac.
011b = WD Timer Event input to the Reset Mux block causes NMI input to C66x CorePac.
100b = WD Timer Event input to the Reset Mux block causes NMI input followed by local reset input to C66x
CorePac. Delay between NMI and local reset is set in DELAY bit field.
110b = Reserved
111b = Reserved
0 LOCK Lock register fields
0 = Register fields are not locked (default)
1 = Register fields are locked until the next timer reset
Table 9-50. Reset Mux Register 8 and 9 (RSTMUX8-RSTMUX9) Field Descriptions
Bit Field Description
31-10 Reserved Reserved
9 EVTSTATCLR Clear event status
0 = Writing 0 has no effect
1 = Writing 1 to this bit clears the EVTSTAT bit
8 Reserved Reserved
7-5 DELAY Delay cycles between NMI & local reset
000b = 256 SYSCLK1/6 cycles delay between interrupt and device reset, when OMODE = 100b
001b = 512 SYSCLK1/6 cycles delay between interrupt and device reset, when OMODE = 100b
010b = 1024 SYSCLK1/6 cycles delay between interrupt and device reset, when OMODE = 100b
011b = 2048 SYSCLK1/6 cycles delay between interrupt and device reset, when OMODE = 100b
100b = 4096 SYSCLK1/6 cycles delay between interrupt and device reset, when OMODE = 100b (default)
101b = 8192 SYSCLK1/6 cycles delay between interrupt and device reset, when OMODE = 100b
110b = 16384 SYSCLK1/6 cycles delay between interrupt and device reset, when OMODE = 100b
111b = 32768 SYSCLK1/6 cycles delay between interrupt and device reset, when OMODE = 100b
4 EVTSTAT Event status
0 = No event received (Default)
1 = WD timer event received by Reset Mux block
Copyright © 2015, Texas Instruments Incorporated Device Boot and Configuration 197
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