66AK2L06
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SPRS930 –APRIL 2015
Figure 9-34. Timer Input Selection Register (TINPSEL3) for Timer 12-Timer15
31 30 28 27 26 24
Reserved TINPHSEL15 Reserved TINPLSEL15
R-0 RW-0 R-0 RW-0
23 22 20 19 18 16
Reserved TINPHSEL14 Reserved TINPLSEL14
R-0 RW-0 R-0 RW-0
15 14 12 11 10 8
Reserved TINPHSEL13 Reserved TINPLSEL13
R-0 RW-0 R-0 RW-0
7 6 4 3 2 0
Reserved TINPHSEL12 Reserved TINPLSEL12
R-0 RW-0 R-0 RW-0
Legend: R = Read only; RW = Read/Write; -n = value after reset
Figure 9-35. Timer Input Selection Register (TINPSEL4) for Timer 16-Timer17
31 16
Reserved
R-0
15 14 12 11 10 8
Reserved TINPHSEL17 Reserved TINPLSEL17
R-0 RW-0 R-0 RW-0
7 6 4 3 2 0
Reserved TINPHSEL16 Reserved TINPLSEL16
R-0 RW-0 R-0 RW-0
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 9-47. Timer Input Selection Field Description
Bit Field Description
31-15 Reserved
11
7
3
14-12 TINPHSELx5 Input select for TIMER16 high and TIMER17 high.
6-4
10-8 TINPLSELx5 Input select for TIMER16 low and TIMER17 low.
2-0
9.2.3.20 Timer Output Selection Register (TOUTPSELx)
The control register TOUTSELx handles the timer output selection and is shown in Figure 9-36 and
Figure 9-37 and described in Table 9-48.
Figure 9-36. Timer Output Selection 0 Register (TOUTPSEL0)
31 30 29 24 23 22 21 16 15 14 13 8 7 6 5 0
Reserved TOUTPSEL3 Reserved TOUTPSEL2 Reserved TOUTPSEL1 Reserved TOUTPSEL0
R-0 RW-010001 R-0 RW-010000 R-0 RW-010101 R-0 RW-010100
Legend: R = Read only; RW = Read/Write; -n = value after reset
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