66AK2L06
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SPRS930 –APRIL 2015
Figure 9-25. Power State Control Register (PWRSTATECTL)
31 3 2 1 0
Hibernation Recovery Branch Address Hibernation Mode Hibernation Standby
RW-0000 0000 0000 0000 0 RW-0 RW-0 RW-0
Legend: R = Read Only, RW = Read/Write; -n = value after reset
Table 9-41. Power State Control Register Field Descriptions
Bit Field Description
31-3 Hibernation Used to provide a start address for execution out of the hibernation modes. See the KeyStone Architecture
Recovery Branch DSP Bootloader User's Guide (SPRUGY5).
Address
2 Hibernation Mode Indicates whether the device is in hibernation mode 1 or mode 2.
• 0 = Hibernation mode 1
• 1 = Hibernation mode 2
1 Hibernation Indicates whether the device is in hibernation mode or not.
• 0 = Not in hibernation mode
• 1 = Hibernation mode
0 Standby Indicates whether the device is in standby mode or not.
• 0 = Not in standby mode
• 1 = standby mode
9.2.3.14 NMI Event Generation to C66x CorePac (NMIGRx) Register
NMIGRx registers generate NMI events to the corresponding C66x CorePac. The 66AK2L06 has four
NMIGRx registers (NMIGR0 through NMIGR3). The NMIGR0 register generates an NMI event to C66x
CorePac0. Writing a 1 to the NMIG field generates an NMI pulse. Writing a 0 has no effect and Reads
return 0 and have no other effect. The NMI event generation to the C66x CorePac is shown in Figure 9-26
and described in Table 9-42.
Figure 9-26. NMI Generation Register (NMIGRx)
31 1 0
Reserved NMIG
R-0000 0000 0000 0000 0000 0000 0000 000 RW-0
Legend: RW = Read/Write; -n = value after reset
Table 9-42. NMI Generation Register Field Descriptions
Bit Field Description
31-1 Reserved Reserved
0 NMIG Reads return 0
Writes:
• 0 = No effect
• 1 = Creates NMI pulse to the corresponding C66x CorePac — C66x CorePac0 for NMIGR0, etc.
9.2.3.15 IPC Generation (IPCGRx) Registers
The IPCGRx Registers facilitate inter-C66x CorePac interrupts.
The 66AK2L06 device has six IPCGRx registers (IPCGR0 through IPCGR3 and IPCGR8 and IPCGR9).
These registers can be used by external hosts or CorePacs to generate interrupts to other CorePacs. A
write of 1 to the IPCG field of the IPCGRx register generates an interrupt pulse to the:
• C66x CorePacx (0 <= x <= 3)
• ARM CorePac core (8<=x<=9)
Copyright © 2015, Texas Instruments Incorporated Device Boot and Configuration 191
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