66AK2L06
SPRS930 –APRIL 2015
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9.2.3.12 Post Boot Disable Registers
9.2.3.12.1 UARTx Post Boot Disable Registers (UARTx_DISABLE)
UART[3:0] peripherals can be disabled post-boot by setting the corresponding UARTx_DISABLE.
These register bits are “sticky” bits, that is they can be set to “1” only once by the software after POR and
they will be cleared to “0” only on POR. In other words, the software is only allowed to switch from
peripheral enabled to disabled state once and not from disabled to enabled state. This feature will be used
in the secondary bootloader to disable the UARTx peripherals for security precaution.
Figure 9-23. UARTx Post Boot Disable Registers (UARTx_DISABLE)
31 1 0
Reserved DISABLE
R-0 RW-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-39. UARTx Post Boot Disable Registers Field Descriptions
Bit Field Description
31-1 Reserved
0 DISABLE UART port disable
• 0 = UART port is enabled (default)
• 1 = UART port is disabled
9.2.3.12.2 USB Post Boot Disable Registers (USB_DISABLE)
USB peripheral can be disabled post-boot by setting the corresponding USB_DISABLE.
This register bit is “sticky” bit, that is it can be set to “1” only once by the software after POR and it will be
cleared to “0” only on POR. In other words, the software is only allowed to switch from peripheral enabled
to disabled state once and not from disabled to enabled state. This feature will be used in the secondary
bootloader to disable the USB peripherals for security precaution.
Figure 9-24. USB Post Boot Disable Registers (USB_DISABLE)
31 1 0
Reserved DISABLE
R-0 RW-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-40. USB Post Boot Disable Registers Field Descriptions
Bit Field Description
31-1 Reserved
0 DISABLE USB port disable
• 0 = USB port is enabled (default)
• 1 = USB port is disabled
9.2.3.13 Power State Control (PWRSTATECTL) Register
The Power State Control Register (PWRSTATECTL) is controlled by the software to indicate the power-
saving mode. Under ROM code, the CorePac reads this register to differentiate between the various
power saving modes. This register is cleared only by POR and is not changed by any other device reset.
See the Hardware Design Guide for KeyStone II Devices application report (SPRABV0) for more
information. The PWRSTATECTL register is shown in Figure 9-25 and described in Table 9-41.
190 Device Boot and Configuration Copyright © 2015, Texas Instruments Incorporated
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