66AK2L06
SPRS930 –APRIL 2015
www.ti.com
9.2.3.4 JTAG ID (JTAGID) Register Description
The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the
device, the JTAG ID register resides at address location 0x02620018. The JTAG ID Register is shown
below.
Figure 9-16. JTAG ID (JTAGID) Register
31 28 27 12 11 1 0
VARIANT PART NUMBER MANUFACTURER LSB
R-xxxx R-1011 1001 1010 0111 R-0000 0010 111 R-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-32. JTAG ID Register Field Descriptions
Bit Field Value Description
31-28 VARIANT xxxx Variant value
27-12 PART NUMBER 1011 1001 1010 0111 Part Number for boundary scan
11-1 MANUFACTURER 0000 0010 111 Manufacturer
0 LSB 1 This bit is read as a 1
NOTE
The value of the VARIANT and PART NUMBER fields depends on the silicon revision being
used. See the Silicon Errata for details.
9.2.3.5 Kicker Mechanism (KICK0 and KICK1) Register
The Bootcfg module contains a kicker mechanism to prevent spurious writes from changing any of the
Bootcfg MMR (memory mapped registers) values. When the kicker is locked (which it is initially after
power on reset), none of the Bootcfg MMRs are writable (they are only readable). This mechanism
requires an MMR write to each of the KICK0 and KICK1 registers with exact data values before the kicker
lock mechanism is unlocked. See Table 9-26 for the address location. Once released, all the Bootcfg
MMRs having write permissions are writable (the read only MMRs are still read only). The KICK0 data is
0x83e70b13. The KICK1 data is 0x95a4f1e0. Writing any other data value to either of these kick MMRs
locks the kicker mechanism and blocks writes to Bootcfg MMRs. To ensure protection to all Bootcfg
MMRs, software must always re-lock the kicker mechanism after completing the MMR writes.
9.2.3.6 LRESETNMI PIN Status (LRSTNMIPINSTAT) Register
The LRSTNMIPINSTAT Register latches the status of LRESET and NMI. The LRESETNMI PIN Status
Register is shown in the figure and table below.
Figure 9-17. LRESETNMI PIN Status Register (LRSTNMIPINSTAT)
31 12 11 10 9 8 7 4 3 2 1 0
Reserved NMI3 NMI2 NMI1 NMI0 Reserved LR3 LR2 LR1 LR0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
Legend: R = Read only; -n = value after reset
Table 9-33. LRESETNMI PIN Status Register Field Descriptions
Bit Field Description
31-12 Reserved Reserved
11 NMI3 C66x CorePac3 in NMI
10 NMI2 C66x CorePac2 in NMI
9 NMI1 C66x CorePac1 in NMI
186 Device Boot and Configuration Copyright © 2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: 66AK2L06
