66AK2L06
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SPRS930 –APRIL 2015
Table 9-31. Pin Mux Control 2 Register Field Descriptions (continued)
Bit Field Description
13 GPIO_EMIFA_SEL[13]
• 0 - Select EMIFA15(Default)
• 1 - Select GPIO45
12 GPIO_EMIFA_SEL[12]
• 0 - Select EMIFA14 (Default)
• 1 - Select GPIO44
11 GPIO_EMIFA_SEL[11]
• 0 - Select EMIFA13 (Default)
• 1 - Select GPIO43
10 GPIO_EMIFA_SEL[10]
• 0 - Select EMIFA10 (Default)
• 1 - Select GPIO42
9 GPIO_EMIFA_SEL[9]
• 0 - Select EMIFA09 (Default)
• 1 - Select GPIO41
8 GPIO_EMIFA_SEL[8]
• 0 - Select EMIFA08 (Default)
• 1 - Select GPIO40
7 GPIO_EMIFA_SEL[7]
• 0 - Select EMIFA07 (Default)
• 1 - Select GPIO39
6 GPIO_EMIFA_SEL[6]
• 0 - Select EMIFA06 (Default)
• 1 - Select GPIO38
5 GPIO_EMIFA_SEL[5]
• 0 - Select EMIFA05 (Default)
• 1 - Select GPIO37
4 GPIO_TIMIO_SEL[4]
• 0 - Select EMIFA04 (Default)
• 1 - Select GPIO36
3 GPIO_TIMIO_SEL[3]
• 0 - Select EMIFA03 (Default)
• 1 - Select GPIO35
2 GPIO_TIMIO_SEL[2]
• 0 - Select EMIFA02 (Default)
• 1 - Select GPIO34
1 GPIO_TIMIO_SEL[2]
• 0 - Select EMIFA01 (Default)
• 1 - Select GPIO33
0 GPIO_TIMIO_SEL[0]
• 0 - Select EMIFA00 (Default)
• 1 - Select GPIO32
Copyright © 2015, Texas Instruments Incorporated Device Boot and Configuration 185
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