66AK2L06
SPRS930 –APRIL 2015
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9.2.3.3.3 Pin Mux Control 2 Register (PIN_MUXCTL2)
The Pin Mux Control 1 Register is shown in Figure 9-14 and described in Table 9-30.
Figure 9-15. Pin Mux Control 2 Register (PIN_MUXCTL2 )
31 16 15 0
GPIO_DFEIO_SEL GPIO_EMIFA_SEL
R/W-0 R/W-0
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 9-31. Pin Mux Control 2 Register Field Descriptions
Bit Field Description
31 GPIO_DFEIO_SEL[31]
• 0 - Select DFEIO17 (Default)
• 1 - Select GPIO63
30 GPIO_DFEIO_SEL[30]
• 0 - Select DFEIO16 (Default)
• 1 - Select GPIO62
29 GPIO_DFEIO_SEL[29]
• 0 - Select DFEIO15 (Default)
• 1 - Select GPIO61
28 GPIO_DFEIO_SEL[28]
• 0 - Select DFEIO14(Default)
• 1 - Select GPIO60
27 GPIO_DFEIO_SEL[27]
• 0 - Select DFEIO13 (Default)
• 1 - Select GPIO59
26 GPIO_DFEIO_SEL[26]
• 0 - Select DFEIO12 (Default)
• 1 - Select GPIO58
25 GPIO_DFEIO_SEL[25]
• 0 - Select DFEIO11 (Default)
• 1 - Select GPIO57
24 GPIO_DFEIO_SEL[24]
• 0 - Select DFEIO10 (Default)
• 1 - Select GPIO56
23 GPIO_DFEIO_SEL[23]
• 0 - Select DFEIO9 (Default)
• 1 - Select GPIO55
22 GPIO_DFEIO_SEL[22]
• 0 - Select DFEIO8 (Default)
• 1 - Select GPIO54
21 GPIO_DFEIO_SEL[21]
• 0 - Select DFEIO7 (Default)
• 1 - Select GPIO53
20 GPIO_DFEIO_SEL[20]
• 0 - Select DFEIO6 (Default)
• 1 - Select GPIO52
19 GPIO_DFEIO_SEL[19]
• 0 - Select DFEIO5 (Default)
• 1 - Select GPIO51
18 GPIO_DFEIO_SEL[18]
• 0 - Select DFEIO4 (Default)
• 1 - Select GPIO50
17 GPIO_DFEIO_SEL[17]
• 0 - Select DFEIO3 (Default)
• 1 - Select GPIO49
16 GPIO_DFEIO_SEL[16]
• 0 - Select DFEIO2 (Default)
• 1 - Select GPIO48
15 GPIO_EMIFA_SEL[15]
• 0 - Select EMIFA17 (Default)
• 1 - Select GPIO47
14 GPIO_EMIFA_SEL[14]
• 0 - Select EMIFA16 (Default)
• 1 - Select GPIO46
184 Device Boot and Configuration Copyright © 2015, Texas Instruments Incorporated
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