66AK2L06
SPRS930 –APRIL 2015
www.ti.com
Table 9-29. Pin Mux Control 0 Register Field Descriptions (continued)
Bit Field Description
5-4 UART2_EMIFA_SEL
• 00 - Select EMIF A18-A21 (Default)
• 01 - Select UART2 without flow control (RXD, TXD only) and EMIF A18-19
• 10 - Reserved
• 11 - Select UART2 with flow control
3 Reserved Reserved. Read only, writes have no effect.
2 UART01_SPI2_SEL
• 0 - Select UART0 and UART1 flow control signals (UART0CTS, UART0RTS, UART1CTS and
UART1RTS) (Default)
• 1 - Select SPI2 with CS0 (SPI2CLK, SPI2CS0, SPI2SOMI, SPI2SIMO)
1 DFESYNC_RP1_SEL
• 0 - Select DFE_SYNC_IN0 and DFE_SYNC_IN_1(Default)
• 1 - Select SRP1CLK and RP1FB
0 AVSIF_SEL
• 0 - Select CVNTL4-5 (Default)
• 1 - Select SmartReflex I2C port (VCL and VD pins)
9.2.3.3.2 Pin Mux Control 1 Register (PIN_MUXCTL1)
The Pin Mux Control 1 Register is shown in Figure 9-14 and described in Table 9-30.
Figure 9-14. Pin Mux Control 1 Register (PIN_MUXCTL1)
31 17 16 15 4 3 0
GPIO_EMU_SEL Rsvd GPIO_TIMIO_SEL GPIO_SPI2CS_SEL
R/W-0 R-0 R/W-0 R/W-0
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 9-30. Pin Mux Control 1 Register Field Descriptions
Bit Field Description
31 GPIO_EMU_SEL[31]
• 0 - Select GPIO31 (Default)
• 1 - Select EMU33
30 GPIO_EMU_SEL[30]
• 0 - Select GPIO30(Default)
• 1 - Select EMU32
29 GPIO_EMU_SEL[29]
• 0 - Select GPIO29 (Default)
• 1 - Select EMU31
28 GPIO_EMU_SEL[28]
• 0 - Select GPIO28(Default)
• 1 - Select EMU30
27 GPIO_EMU_SEL[27]
• 0 - Select GPIO27 (Default)
• 1 - Select EMU29
26 GPIO_EMU_SEL[26]
• 0 - Select GPIO26 (Default)
• 1 - Select EMU28
25 GPIO_EMU_SEL[25]
• 0 - Select GPIO25 (Default)
• 1 - Select EMU27
24 GPIO_EMU_SEL[24]
• 0 - Select GPIO24 (Default)
• 1 - Select EMU26
23 GPIO_EMU_SEL[23]
• 0 - Select GPIO23 (Default)
• 1 - Select EMU25
22 GPIO_EMU_SEL[22]
• 0 - Select GPIO22 (Default)
• 1 - Select EMU24
21 GPIO_EMU_SEL[21]
• 0 - Select GPIO21 (Default)
• 1 - Select EMU23
182 Device Boot and Configuration Copyright © 2015, Texas Instruments Incorporated
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