66AK2L06
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SPRS930 –APRIL 2015
9.2.3.2 Device Configuration Register
The Device Configuration Register is one-time writeable through software. The register is reset on all hard
resets and is locked after the first write. The Device Configuration Register is shown in Figure 9-12 and
described in Table 9-28.
Figure 9-12. Device Configuration Register (DEVCFG)
31 5 4 3 2 1 0
Reserved PCIESS_1_ PCIESS_0_ SYSCLKOUT
MODE MODE EN
R-0 R/W-00 R/W-00 R/W-1
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 9-28. Device Configuration Register Field Descriptions
Bit Field Description
31-5 Reserved Reserved. Read only, writes have no effect.
4-3 PCIESS_1_MODE Device Type Input of PCIeSS_1
• 00 = Endpoint
• 01 = Legacy Endpoint
• 10 = Rootcomplex
• 11 = Reserved
2-1 PCIESS_0_MODE Device Type Input of PCIeSS_0
• 00 = Endpoint
• 01 = Legacy Endpoint
• 10 = Rootcomplex
• 11 = Reserved
0 SYSCLKOUTEN SYSCLKOUT enable
• 0 = No clock output
• 1 = Clock output enabled (default)
9.2.3.3 Pin Mux Control Register
Pin mux control registers are used to control the various pins that are muxed at the chip level.
9.2.3.3.1 Pin Mux Control 0 Register (PIN_MUXCTL0)
The Pin Mux Control 0 Register is shown in Figure 9-13 and described in Table 9-29.
Figure 9-13. Pin Mux Control 0 Register (PIN_MUXCTL0)
31 8 7 6 5 4 3 2 1 0
Reserved UART3_EMIFA UART2_EMIFA Reserved UART01_SPI2_ DFESYNC_RP1_ AVSIF_SEL
_SEL _SEL SEL SEL
R-0 R/W-0 R/W-00 R, 0 R/W-0 R/W-0 R/W-0
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 9-29. Pin Mux Control 0 Register Field Descriptions
Bit Field Description
31-8 Reserved Reserved. Read only, writes have no effect.
7-6 UART3_EMIFA_SEL
• 00 - Select EMIF A22- A23, CE2-CE3 (Default)
• 01 - Select UART3 without flow control (RXD, TXD only) and EMIF CE2 - CE3
• 10 - Reserved
• 11 - Select UART3 with flow control
Copyright © 2015, Texas Instruments Incorporated Device Boot and Configuration 181
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