66AK2L06
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SPRS930 –APRIL 2015
9.2.1 Device Configuration at Device Reset
The logic level present on each device configuration pin is latched at power-on reset to determine the
device configuration. The logic level on the device configuration pins can be set by using external
pullup/pulldown resistors or by using some control device (e.g., FPGA/CPLD) to intelligently drive these
pins. When using a control device, care should be taken to ensure there is no contention on the lines
when the device is out of reset. The device configuration pins are sampled during power-on reset and are
driven after the reset is removed. To avoid contention, the control device must stop driving the device
configuration pins of the SoC. Table 9-25 describes the device configuration pins.
NOTE
If a configuration pin must be routed out from the device and it is not driven (Hi-Z state), the
internal pullup/pulldown (IPU/IPD) resistor should not be relied upon. TI recommends the use
of an external pullup/pulldown resistor. For more detailed information on pullup/pulldown
resistors and situations in which external pullup/pulldown resistors are required, see
Section 6.4.
Table 9-25. Device Configuration Pins
CONFIGURATION PIN PIN NO. IPD/IPU
(1)
DESCRIPTION
LENDIAN
(1)(2)
F29 IPU Device endian mode (LENDIAN)
• 0 = Device operates in big endian mode
• 1 = Device operates in little endian mode
BOOTMODE[15:0]
(1)(2)
B31, E32, A31, F30, IPD Method of boot
E30, F31, G30, A30,
• See Section 9.1.2 for more details.
C30, D30, E29, B29,
• See the KeyStone II Architecture ARM Bootloader User's Guide
A35, D29, B30, F29
(SPRUHJ3) for detailed information on boot configuration.
AVSIFSEL[1:0]
(1)(2)
M1, M2 IPD AVS interface selection
• 00 = AVS 4-pin 6-bit Dual-Phase VCNTL[5:2] (Default)
• 01 = AVS 4-pin 4-bit Single-Phase VCNTL[5:2]
• 10 = AVS 6-pin 6-bit Single-Phase VCNTL[5:0]
• 11 = I
2
C
(1) Internal 100-µA pulldown or pullup is provided for this terminal. In most systems, a 1-kΩ resistor can be used to oppose the IPD/IPU.
For more detailed information on pulldown/pullup resistors and situations in which external pulldown/pullup resistors are required, see
Section 6.4.
(2) These signal names are the secondary functions of these pins.
9.2.2 Peripheral Selection After Device Reset
Several of the peripherals on the 66AK2L06 are controlled by the Power Sleep Controller (PSC). By
default, the PCIe, FFTC, and AIF2 are held in reset and clock-gated. The memories in these modules are
also in a low-leakage sleep mode. Software is required to turn these memories on. Then, the software
enables the modules (turns on clocks and de-asserts reset) before these modules can be used.
If one of the above modules is used in the selected ROM boot mode, the ROM code automatically
enables the module.
All other modules come up enabled by default and there is no special software sequence to enable. For
more detailed information on the PSC usage, see the KeyStone Architecture Power Sleep Controller
(PSC) User's Guide (SPRUGV4).
9.2.3 Device State Control Registers
The 66AK2L06 device has a set of registers that are used to control the status of its peripherals. These
registers are shown in Table 9-26.
Copyright © 2015, Texas Instruments Incorporated Device Boot and Configuration 175
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