66AK2L06
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SPRS930 –APRIL 2015
Table 9-22. DDR3 Boot Parameter Table (continued)
CONFIGURED
BYTE THROUGH BOOT
OFFSET NAME DESCRIPTION CONFIGURATION PINS
20 pllPostDiv PLL post divider value (Should be the exact value not value -1) NO
24 sdRamConfig SDRAM config register NO
28 sdRamConfig2 SDRAM Config register NO
32 sdRamRefreshctl SDRAM Refresh Control Register NO
36 sdRamTiming1 SDRAM Timing 1 Register NO
40 sdRamTiming2 SDRAM Timing 2 Register NO
44 sdRamTiming3 SDRAM Timing 3 Register NO
48 IpDfrNvmTiming LP DDR2 NVM Timing Register NO
52 powerMngCtl Power management Control Register NO
56 iODFTTestLogic IODFT Test Logic Global Control Register NO
60 performcountCfg Performance Counter Config Register NO
64 performCountMstRegSel Performance Counter Master Region Select Register NO
68 readIdleCtl Read IDLE counter Register NO
72 sysVbusmIntEnSet System Interrupt Enable Set Register NO
76 sdRamOutImpdedCalcfg SDRAM Output Impedence Calibration Config Register NO
80 tempAlertCfg Temperature Alert Configuration Register NO
84 ddrPhyCtl1 DDR PHY Control Register 1 NO
88 ddrPhyCtl2 DDR PHY Control Register 1 NO
92 proClassSvceMap Priority to Class of Service mapping Register NO
96 mstId2ClsSvce1Map Master ID to Class of Service Mapping 1 Register NO
100 mstId2ClsSvce2Map Master ID to Class of Service Mapping 2Register NO
104 eccCtl ECC Control Register NO
108 eccRange1 ECC Address Range1 Register NO
112 eccRange2 ECC Address Range2 Register NO
116 rdWrtExcThresh Read Write Execution Threshold Register NO
120 - 376 Chip Config Chip Specific PHY configuration NO
9.1.2.5 Second-Level Bootloaders
Any of the boot modes can be used to download a second-level bootloader. A second-level bootloader
allows for:
• Any level of customization to current boot methods
• Definition of a completely customized boot
9.1.3 System PLL Settings
The PLL default settings are determined by the BOOTMODE[7:5] bits. Table 9-23 shows the settings for
various input clock frequencies. This will set the PLL to the maximum clock setting for the device.
CLK = CLKIN × ((PLLM+1) ÷ ((OUTPUT_DIVIDE+1) × (PLLD+1)))
Where OUTPUT_DIVIDE is the value of the field of SECCTL[22:19]
NOTE
Other frequencies are supported, but require a boot in a pre-configured mode.
Copyright © 2015, Texas Instruments Incorporated Device Boot and Configuration 173
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