66AK2L06
SPRS930 –APRIL 2015
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Table 9-20. UART Boot Parameter Table (continued)
CONFIGURED THROUGH
BYTE BOOT CONFIGURATION
OFFSET NAME DESCRIPTION PINS
44 Flow Control Bits 00 Flow Control NO
• 0 = No Flow Control
• 1 = RTS_CTS flow control
Bits 15 - 01 Reserved
46 Data Rate MSW Baud Rate, MSW NO
48 Data Rate LSW Baud Rate, LSW NO
50 Blob Base, MSW For blob format, base address, MSW NO
52 Blob Base, LSW For blob format, base address, LSW NO
9.1.2.4.7 NAND Boot Parameter Table
Table 9-21. NAND Boot Parameter Table
CONFIGURED THROUGH
BYTE OFFSET NAME DESCRIPTION BOOT CONFIGURATION PINS
22 Options Bits 00 Geometry NO
• 0 = Geometry is taken from this table
• 1 = Geometry is queried from NAND device.
Bits 01 Clear NAND
• 0 = NAND Device is a non clear NAND and
requires ECC
• 1 = NAND is a clear NAND and doesn.t need
ECC.
Bits 15 - 02 Reserved
24 numColumnAddrBytes Number of bytes used to specify column address NO
26 numRowAddrBytes Number of bytes used to specify row address. NO
28 numofDataBytesperPage_msw Number of data bytes in each page, MSW NO
30 numofDataBytesperPage_lsw Number of data bytes in each page, LSW NO
32 numPagesperBlock Number of Pages per Block NO
34 busWidth EMIF bus width. Only 8 or 16 bits is supported. NO
36 numSpareBytesperPage Number of spare bytes allocated per page. NO
38 csel Chip Select number (valid chip selects are 2-5) YES
40 First Block First block for RBL to try to read. YES
9.1.2.4.8 DDR3 Configuration Table
The RBL also provides an option to configure the DDR table before loading the image into the external
memory. More information on how to configure the DDR3, refer to the Bootloader User Guide. The
configuration table for DDR3 is shown in Table 9-22
Table 9-22. DDR3 Boot Parameter Table
CONFIGURED
BYTE THROUGH BOOT
OFFSET NAME DESCRIPTION CONFIGURATION PINS
0 configselect msw Selecting the configuration register below that to be set. Each NO
filed below is represented by one bit each.
4 configselect slsw Selecting the configuration register below that to be set. Each NO
filed below is represented by one bit each.
8 configselect lsw Selecting the configuration register below that to be set. Each NO
filed below is represented by one bit each.
12 pllprediv PLL pre divider value (Should be the exact value not value -1) NO
16 pllMult PLL Multiplier value (Should be the exact value not value -1) NO
172 Device Boot and Configuration Copyright © 2015, Texas Instruments Incorporated
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