66AK2L06
SPRS930 –APRIL 2015
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Table 9-17. PCIe Boot Parameter Table (continued)
CONFIGURED
BYTE THROUGH BOOT
OFFSET NAME DESCRIPTION CONFIGURATION PINS
28 Reference clock Reference clock frequency, in units of 10 kHz. Value values are 10000 NO
(100 MHz), 12500 (125 MHz), 15625 (156.25 MHz), 25000 (250 MHz)
and 31250 (312.5 MHz). A value of 0 means that value is already in
the SerDes cfg parameters and will not be computed by the boot
ROM.
30 Window 1 Size Window 1size. YES
32 Window 2 Size Window 2 size. YES
34 Window 3 Size Window 3 size. Valid only if address width is 32. YES
36 Window 4 Size Window 4 Size. Valid only if the address width is 32. YES
38 Window 5 Size Window 5 Size. Valid only if the address width is 32. NO
40 Vendor ID Vendor ID NO
42 Device ID Device ID NO
44 Class code Rev ID Class code revision ID MSW NO
MSW
46 Class code Rev ID Class code revision ID LSW NO
LSW
60 Timeout period (Secs) The timeout period. Values 0 disables the time out
9.1.2.4.4 I
2
C Boot Parameter Table
Table 9-18. I
2
C Boot Parameter Table
CONFIGURED
THROUGH BOOT
OFFSET FIELD VALUE CONFIGURATION PINS
22 Option Bits 02 - 00 Mode NO
• 000 = Boot Parameter Table Mode
• 001 = Boot Table Mode
• 010 = Boot Config Mode
• 011 = Load GP header format data
• 100 = Slave Receive Boot Config
Bits 15 - 03= Reserved
24 Boot Dev Addr The I
2
C device address to boot from YES
26 Boot Dev Addr Ext Extended boot device address YES
28 Broadcast Addr I
2
C address used to send data in the I
2
C master NO
broadcast mode.
30 Local Address The I
2
C address of this device NO
32 Bus Frequency The desired I
2
C data rate (kHz) NO
34 Next Dev Addr The next device address to boot (Used only if boot NO
config option is selected)
36 Next Dev Addr Ext The extended next device address to boot (Used only NO
if boot config option is selected)
38 Address Delay The number of CPU cycles to delay between writing NO
the address to an I
2
C EEPROM and reading data.
170 Device Boot and Configuration Copyright © 2015, Texas Instruments Incorporated
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