66AK2L06
www.ti.com
SPRS930 –APRIL 2015
Table 9-6. I
2
C Master Mode Device Configuration Field Descriptions (continued)
Bit Field Description
10-9 Bus Addr I
2
C bus address slave device
• 0 = I
2
C slave boot bus address is 0x50 (default)
• 1 = I
2
C slave boot bus address is 0x51
• 2 = I
2
C slave boot bus address is 0x52
• 3 = I
2
C slave boot bus address is 0x53
8 Boot Master Boot Master select
• 0 = ARM is boot master
• 1 = C66x is boot master
7 Reserved Reserved
6-5 Port I
2
C port number
• 0 = I
2
C0 (default)
• 1 = I
2
C1
• 2 = I
2
C2
• 3 = Reserved
4 Min Minimum boot configuration select bit.
• 0 = Minimum boot pin select disabled
• 1 = Minimum boot pin select enabled.
When Min = 1, a predetermined set of values is configured (see the Device Configuration Field Descriptions table
for configuration bits with a "(default)" tag added in the description column).
When Min = 0, all fields must be independently configured.
3-1 Boot Devices Boot Devices[3:1]
• 010 = I
2
C Master
• Others = Other boot modes
0 Lendian Endianess
• 0 = Big endian
• 1 = Little endian
9.1.2.2.3 SPI Boot Device Configuration
Figure 9-5. SPI Device Configuration Fields
DEVSTAT Boot Mode Pins ROM Mapping
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Width1 Mode Param ldx/Offset Csel Boot Master Width0 Port Min 011 Lendian
Table 9-7. SPI Device Configuration Field Descriptions
Bit Field Description
16-7 Width1:Width0 SPI address width configuration
• 00 = 16-bit address values are used
• 01 = 24-bit address values are used (default)
• 01 = 32-bit address values are used
• 11 = 32-bit address values are used
15-14 Mode Clk Polarity/ Phase
• 0 = Data is output on the rising edge of SPICLK. Input data is latched on the falling edge.
• 1 = Data is output one half-cycle before the first rising edge of SPICLK and on subsequent falling
edges. Input data is latched on the rising edge of SPICLK.
• 2 = Data is output on the falling edge of SPICLK. Input data is latched on the rising edge (default).
• 3 = Data is output one half-cycle before the first falling edge of SPICLK and on subsequent rising
edges. Input data is latched on the falling edge of SPICLK.
13-11 Param Idx/Offset Parameter Table Index: 0-7
This value specifies the parameter table index when the C66x is the boot master
This value specifies the start read address at 8K times this value when the ARM is the boot master
Copyright © 2015, Texas Instruments Incorporated Device Boot and Configuration 161
Submit Documentation Feedback
Product Folder Links: 66AK2L06
