66AK2L06
SPRS930 –APRIL 2015
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Table 9-5. I
2
C Passive Mode Device Configuration Field Descriptions
Bit Field Description
16-15 Slave Addr I
2
C Slave boot bus address
• 0 = I
2
C slave boot bus address is 0x00
• 1 = I
2
C slave boot bus address is 0x10 (default)
• 2 = I
2
C slave boot bus address is 0x20
• 3 = I
2
C slave boot bus address is 0x30
14 Boot Devices Boot Device[14] used in conjunction with Boot Devices [Used in conjunction with bits 3-1]
• 0 = Other boot modes
• 1= I
2
C Slave boot mode
13-12 Port I
2
C port number
• 0 = I
2
C0
• 1 = I
2
C1
• 2 = I
2
C2
• 3 = Reserved
11-9 ARM PLL The PLL default settings are determined by the [11:9] bits. This will set the PLL to the maximum clock setting for
Setting the device. Table 9-23 shows settings for various input clock frequencies.
8 Boot Master Boot Master select
• 0 = ARM is boot master
• 1 = C66x is boot master
7-5 SYS PLL The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock setting for
Setting the device. Table 9-23 shows settings for various input clock frequencies.
4 Min Minimum boot configuration select bit.
• 0 = Minimum boot pin select disabled
• 1 = Minimum boot pin select enabled.
When Min = 1, a predetermined set of values is configured (see the Device Configuration Field Descriptions table
for configuration bits with a "(default)" tag added in the description column).
When Min = 0, all fields must be independently configured.
3-1 Boot Devices Boot Devices[3:1] used in conjunction with Boot Device [14]
• 000 = I
2
C Slave
• Others = Other boot modes
0 Lendian Endianess
• 0 = Big endian
• 1 = Little endian
9.1.2.2.2.2 I
2
C Master Mode
In master mode, the I
2
C device configuration uses ten bits of device configuration instead of seven as
used in other boot modes. In this mode, the device makes the initial read of the I
2
C EEPROM while the
PLL is in bypass mode. The initial read contains the desired clock multiplier, which must be set up prior to
any subsequent reads.
Figure 9-4. I
2
C Master Mode Device Configuration Fields
DEVSTAT Boot Mode Pins ROM Mapping
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved Param ldx/Offset Bus Addr Boot Master Reserved Port Min 010 Lendian
Table 9-6. I
2
C Master Mode Device Configuration Field Descriptions
Bit Field Description
16-14 Reserved Reserved
13-11 Param Parameter Table Index: 0-7
Idx/Offset
This value specifies the parameter table index when the C66x is the boot master
This value specifies the start read address at 8K times this value when the ARM is the boot master
160 Device Boot and Configuration Copyright © 2015, Texas Instruments Incorporated
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