66AK2L06
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SPRS930 –APRIL 2015
9.1.2.2 Device Configuration Field
The device configuration fields DEVSTAT[16:1] are used to configure the boot peripheral and, therefore,
the bit definitions depend on the boot mode.
9.1.2.2.1 Sleep Boot Mode Configuration
Figure 9-2. Sleep Boot Mode Configuration Fields Description
DEVSTAT Boot Mode Pins ROM Mapping
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Boot
X X X ARMen SYSEN ARM PLL Cfg Sys PLL Config Min 000 Lendian
Master
Table 9-4. Sleep Boot Configuration Field Descriptions
Bit Field Description
16-14 Reserved Reserved
13 ARMen Enable the ARM PLL
• 0 = PLL disabled
• 1 = PLL enabled
12 SYSEN Enable the System PLL
• 0 = PLL disabled (default)
• 1 = PLL enabled
11-9 ARM PLL The PLL default settings are determined by the [11:9] bits. This will set the PLL to the maximum clock setting for
Setting the device. Table 9-23 shows settings for various input clock frequencies.
8 Boot Master Boot Master select
• 0 = ARM is boot master
• 1 = C66x is boot master
7-5 SYS PLL The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock setting for
Setting the device. Table 9-23 shows settings for various input clock frequencies.
4 Min Minimum boot configuration select bit.
• 0 = Minimum boot pin select disabled
• 1 = Minimum boot pin select enabled.
When Min = 1, a predetermined set of values is configured (see the Device Configuration Field Descriptions table
for configuration bits with a "(default)" tag added in the description column).
When Min = 0, all fields must be independently configured.
3-1 Boot Devices Boot Devices[3:1] used in conjunction with Boot Device [14]
• 000 = Sleep
• Others = Other boot modes
0 Lendian Endianess (device)
• 0 = Big endian
• 1 = Little endian
9.1.2.2.2 I
2
C Boot Device Configuration
9.1.2.2.2.1 I
2
C Passive Mode
In passive mode, the device does not drive the clock, but simply acks data received on the specified
address.
Figure 9-3. I
2
C Passive Mode Device Configuration Fields
DEVSTAT Boot Mode Pins ROM Mapping
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Boot
Slave Addr 1 Port ARM PLL Cfg Sys PLL Config Min 000 Lendian
Master
Copyright © 2015, Texas Instruments Incorporated Device Boot and Configuration 159
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