66AK2L06
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SPRS930 –APRIL 2015
Table 9-2. ARM Boot RAM Memory Map (continued)
START ADDRESS SIZE DESCRIPTION
0x0c1d_9fe0 0x2020 ARM0 Boot Trace data
0x0c1d_c000 0x180 ARM1
(1)
Version info
0x0c1d_c180 0x80 ARM1 Boot progress stack
0x0c1d_c200 0x100 ARM1 Boot stats
0x0c1d_c300 0x100 ARM1 Boot Log data
0x0c1d_c400 0x100 ARM1 RAM Call tables
0x0c1d_c500 0x100 RAM1 Boot Parameter tables
0x0c1d_c600 0x99e0 ARM1 Local core Boot data
0x0c1d_cfe0 0x2020 ARM1 Boot Trace data
0xc0c1e_0000 0x4000 ARM0 Secure Load data
0xc0c1e_4000 0x2ab0 ARM0 Secure Boot data
0xc0c1e_6ab0 0x1550 ARM0 Secure Stack
0xc0c1e_8000 0x4000 ARM1 Secure Load data
0xc0c1e_c000 0x2ab0 ARM1 Secure Boot data
0xc0c1e_eab0 0x1550 ARM1 Secure Stack
(1) The addresses shown for core 1 are the physical addresses. Boot ROM enables the non-secure MMU during the boot process, and the
physical memory shown for ARM core 1(non-secure area) is mapped to the same virtual addresses used by core 0. Core 0 has a flat
map. Likewise for the secure MMU in the secure memory region. When the non-secure boot ROM exits normally the non-secure MMU
is disabled, and for non-secure devices the secure MMU is disabled as well.
9.1.2 Boot Modes Supported
The device supports several boot processes, which leverage the internal boot ROM. Most boot processes
are software-driven, using the BOOTMODE[15:0] device configuration inputs to determine the software
configuration that must be completed. From a hardware perspective, there are two possible boot modes:
• Public ROM Boot when the C6xx CorePac0 is the boot master — The C66x CorePac is released
from reset and begins executing from the L3 ROM base address. The ARM CorePac is also released
from reset at the same time as the C66xCorePac. Both the C66x CorePac and the ARM CorePac read
the bootmode register inside the bootCFG module to determine which is the boot master.
After the Boot ROM for the Cortex-A15 processor reads the bootmode to determine that the C66x
CorePac is the boot master, all Cortex-A15 processors stay idle by executing WFI instruction and
waiting for the C66x CorePac’s interrupt. The chip Boot ROM reads the bootmode register to
determine that the C66x CorePac0 is the boot master, then the C66x CorePac0 performs the boot
process and the other C66x CorePacs execute an IDLE instruction. After the boot process is
completed, the C66x CorePac0 begins to execute the code downloaded during the boot process. If the
downloaded code included code for the other C66x cores and/or the Cortex-A15 processor cores, the
downloaded code may contain logic to write the code execution addresses to the boot address register
for the core that is to execute it. The C66x CorePac0 can then generate an interrupt to the core
causing it to execute the code. When they receive the IPC interrupt, the rest of the C66x CorePacs
and the ARM CorePac complete boot management operations and begin executing from the
predefined location in memory.
• Public ROM Boot when the ARM CorePac Core0 is the boot master — The only difference
between this boot mode and when the C66x CorePac is the boot master, is that the ARM CorePac
performs the boot process while the C66x CorePacs execute idle instructions. When the ARM CorePac
Core0 finishes the boot process, it may send interrupts to the C66x CorePacs and Cortex-A15
processor cores through IPC registers. The C66x CorePacs complete the boot management
operations and begin executing from the predefined locations.
Copyright © 2015, Texas Instruments Incorporated Device Boot and Configuration 157
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