TeraNet 3P_A CPU/3
To TeraNet_3P_Tracer
Bridge_12
Bridge_13
Bridge_14
From TeraNet_3_A
CorePac_0
M
M
CorePac_1
CorePac_2
M
M
CorePac_3
TBR_SYS_
ARM_CorePac
Semaphore
S
Tracer_SM
MPU_10
Tracer_QM_CFG2
MPU_6
CP_INTC0/2
S
ARM INTC
S
TNet_3P_L
CPU/3
MPU_9
Tracer_INTC
MPU ( 15)´
S
To TeraNet_3P_B
66AK2L06
TNet_3P_C
CPU/3
Tracer
_EDMA
CC1 - CC3
Tracer_CFG
MPU_0
S
CC2
S
TC ( 4)´
S
CC1
S
TC ( 4)´
TNet_3P_M
CPU/3
Tracer
_EDMA
CC0 & CC4
S
CC0
S
TC ( 2)´
QM_SS_
CFG2
M
Tracer_QM_CFG1
MPU_2
QM_SS_
CFG1
M
DBG_TBR_SYS
(Debug_SS)
TETB
CorePac ( 4)´
From TeraNet_3_C
66AK2L06
www.ti.com
SPRS930 –APRIL 2015
8.3 TeraNet Switch Fabric Connections Matrix - Configuration Space
The figures below show the connections between masters and slaves through various sections of the
TeraNet.
Figure 8-6. TeraNet 3P_A
Copyright © 2015, Texas Instruments Incorporated System Interconnect 147
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