CorePac_0
S
Tracer_L2_0
TNet_3_M
CPU/3
K2L
CorePac_1
S
Tracer_L2_1
TNet_3_N
CPU/3
CorePac_2
S
Tracer_L2_2
TNet_3_O
CPU/3
CorePac_3
S
Tracer_L2_3
TNet_3_P
CPU/3
L2 Cache_0_A
From TeraNet 3_A-2
L2 Cache_0_B
L2 Cache_1_A
L2 Cache_1_B
L2 Cache_2_A
L2 Cache_2_B
L2 Cache_3_A
L2 Cache_3_B
66AK2L06
SPRS930 –APRIL 2015
www.ti.com
Figure 8-5. TeraNet C66x to SDMA
140 System Interconnect Copyright © 2015, Texas Instruments Incorporated
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