TeraNet 3_A-1 CPU/3
Bridge_1
Bridge_2
Bridge_3
From TeraNet_3_C
Bridge_5
Bridge_6
Bridge_7
Bridge_8
To TeraNet_3_C
Bridge_9
Bridge_10
Bridge_12
Bridge_13
Bridge_14
To TeraNet_3P_A
USB_MST
M
TNet_3_D
CPU/3
Debug_SS
M
QM
Packet DMA
M
TNet_3_H
CPU/3
66AK2L06
Boot_ROM
ARM
S
EMIF16
S
SPI_2
S
TNet_6P_A
CPU/6
SPI_1
S
SPI_0
S
MPU_12
MPU_13
MPU_14
MPU_8
Bridge_11
Tracer_SPI_
ROM_EMIF16
FFTC_0
Packet DMA
M
FFTC_1
Packet DMA
M
66AK2L06
SPRS930 –APRIL 2015
www.ti.com
Figure 8-1. TeraNet 3_A-1
136 System Interconnect Copyright © 2015, Texas Instruments Incorporated
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