L1D Memory
00F0 0000h
00F0 4000h
00F0 6000h
00F0 7000h
00F0 8000h
1/2
SRAM
2-Way
Cache
3/4
SRAM
7/8
SRAM
All
SRAM
000 001 010 011 100
Block Base
Address
L1D Mode Bits
4K bytes
8K bytes
16K bytes
4K bytes
2-Way
Cache
2-Way
Cache
2-Way
Cache
66AK2L06
www.ti.com
SPRS930 –APRIL 2015
Figure 4-3. L1D Memory Configurations
4.1.3 L2 Memory
The L2 memory configuration for the 66AK2L06 device is as follows:
• Total memory size is 4096KB
• Each CorePac contains 1024KB of memory
• Local starting address for each CorePac is 0080 0000h
L2 memory can be configured as all SRAM, all 4-way set-associative cache, or a mix of the two. The
amount of L2 memory that is configured as cache is controlled through the L2MODE field of the L2
Configuration Register (L2CFG) of the C66x CorePac. Figure 4-4 shows the available SRAM/cache
configurations for L2. By default, L2 is configured as all SRAM after device reset.
Copyright © 2015, Texas Instruments Incorporated C66x CorePac 13
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