66AK2L06
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SPRS930 –APRIL 2015
• 64 DMA channels for all EDMA3CC
– Manually triggered (CPU writes to channel controller register)
– External event triggered
– Chain triggered (completion of one transfer triggers another)
• 8 Quick DMA (QDMA) channels per EDMA3CCx
– Used for software-driven transfers
– Triggered upon writing to a single PaRAM set entry
• Two transfer controllers and two event queues with programmable system-level priority for
EDMA3CC0, EDMA3CC3 and EDMA3CC4
• Four transfer controllers and four event queues with programmable system-level priority for each of
EDMA3CC1 and EDMA3CC2
• Interrupt generation for transfer completion and error conditions
• Debug visibility
– Queue watermarking/threshold allows detection of maximum usage of event queues
– Error and status recording to facilitate debug
7.4.1 EDMA3 Device-Specific Information
The EDMA supports two addressing modes: constant addressing and increment addressing mode.
Constant addressing mode is applicable to a very limited set of use cases. For most applications
increment mode can be used. For more information on these two addressing modes, see the KeyStone
Architecture Enhanced Direct Memory Access 3 (EDMA3) User's Guide (SPRUGS5).
For the range of memory addresses that includes EDMA3 channel controller (EDMA3CC) control registers
and EDMA3 transfer controller (TPTC) control registers, see Section Section 7.1. For memory offsets and
other details on EDMA3CC and TPTC Control Register entries, see the KeyStone Architecture Enhanced
Direct Memory Access 3 (EDMA3) User's Guide (SPRUGS5).
7.4.2 EDMA3 Channel Controller Configuration
Table 7-30 shows the configuration for each of the EDMA3 channel controllers present on the device.
Table 7-30. EDMA3 Channel Controller Configuration
DESCRIPTION EDMA3 CC0 EDMA3 CC1 EDMA3 CC2
Number of DMA channels in channel controller 64 64 64
Number of QDMA channels 8 8 8
Number of interrupt channels 64 64 64
Number of PaRAM set entries 512 512 512
Number of event queues 2 4 4
Number of transfer controllers 2 4 4
Memory protection existence Yes Yes Yes
Number of memory protection and shadow regions 8 8 8
7.4.3 EDMA3 Transfer Controller Configuration
Each transfer controller on the device is designed differently based on considerations like performance
requirements, system topology (like main TeraNet bus width, external memory bus width), etc. The
parameters that determine the transfer controller configurations are:
• FIFOSIZE: Determines the size in bytes for the data FIFO that is the temporary buffer for the in-flight
data. The data FIFO is where the read return data read by the TC read controller from the source
endpoint is stored and subsequently written out to the destination endpoint by the TC write controller.
• BUSWIDTH: The width of the read and write data buses in bytes, for the TC read and write controller,
respectively. This is typically equal to the bus width of the main TeraNet interface.
Copyright © 2015, Texas Instruments Incorporated Memory, Interrupts, and EDMA for 66AK2L06 129
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