66AK2L06
SPRS930 –APRIL 2015
www.ti.com
Table 7-29. LRESET and NMI Decoding (continued)
CORESEL[3:0] PIN LRESET PIN NMI PIN LRESETNMIEN PIN
INPUT INPUT INPUT INPUT RESET MUX BLOCK OUTPUT
0000 1 1 0 De-assert local reset & NMI to C66x CorePac0
0001 1 1 0 De-assert local reset & NMI to C66x CorePac1
0010 1 1 0 De-assert local reset & NMI to C66x CorePac2
0011 1 1 0 De-assert local reset & NMI to C66x CorePac3
1XXX 1 1 0 De-assert local reset & NMI to all C66x CorePacs
0000 1 0 0 Assert NMI to C66x CorePac0
0001 1 0 0 Assert NMI to C66x CorePac1
0010 1 0 0 Assert NMI to C66x CorePac2
0011 1 0 0 Assert NMI to C66x CorePac3
1XXX 1 0 0 Assert NMI to all C66x CorePacs
7.4 Enhanced Direct Memory Access (EDMA3) Controller for 66AK2L06
The primary purpose of the EDMA3 is to service user-programmed data transfers between two memory-
mapped slave endpoints on the device. The EDMA3 services software-driven paging transfers (e.g., data
movement between external memory and internal memory), performs sorting or subframe extraction of
various data structures, services event driven peripherals, and offloads data transfers from the device
C66x DSP CorePac or the ARM CorePac.
There are 3 EDMA channel controllers on the device:
• EDMA3CC0 has two transfer controllers: TPTC0 and TPTC1
• EDMA3CC1 has four transfer controllers: TPTC0, TPTC1, TPTC2, and TPTC3
• EDMA3CC2 has four transfer controllers: TPTC0, TPTC1, TPTC2, and TPTC3
In the context of this document, TPTCx is associated with EDMA3CCy, and is referred to as EDMA3CCy
TPTCx. Each of the transfer controllers has a direct connection to the switch fabric. Section 8.2 lists the
peripherals that can be accessed by the transfer controllers.
EDMA3CC0 is optimized to be used for transfers to/from/within the MSMC and DDR3A subsytems. The
others are used for the remaining traffic.
Each EDMA3 channel controller includes the following features:
• Fully orthogonal transfer description
– 3 transfer dimensions:
• Array (multiple bytes)
• Frame (multiple arrays)
• Block (multiple frames)
– Single event can trigger transfer of array, frame, or entire block
– Independent indexes on source and destination
• Flexible transfer definition:
– Increment or FIFO transfer addressing modes
– Linking mechanism allows for ping-pong buffering, circular buffering, and repetitive/continuous
transfers, all with no CPU intervention
– Chaining allows multiple transfers to execute with one event
• 512 PaRAM entries for all EDMA3CC
– Used to define transfer context for channels
– Each PaRAM entry can be used as a DMA entry, QDMA entry, or link entry
128 Memory, Interrupts, and EDMA for 66AK2L06 Copyright © 2015, Texas Instruments Incorporated
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