66AK2L06
SPRS930 –APRIL 2015
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Table 7-25. CIC2 Event Inputs (Secondary Events for EDMA3CC0, EDMACC1 and EDMA3CC2) (continued)
EVENT NO. EVENT NAME DESCRIPTION
456 ARM_NCNTPNSIRQ1 ARM NCNTPNSIRQ1
457 ARM_NCNTPNSIRQ0 ARM NCNTPNSIRQ0
458 ARM_TBR_DMA ARM trace buffer (TBR) DMA event
459 Reserved
460 Reserved
461 USB_INT02 USB interrupt
462 USB_INT03 USB interrupt
463 GPIO_INT0 GPIO interrupt
464 GPIO_INT1 GPIO interrupt
465 GPIO_INT2 GPIO interrupt
466 GPIO_INT3 GPIO interrupt
467 GPIO_INT4 GPIO interrupt
468 GPIO_INT5 GPIO interrupt
469 GPIO_INT6 GPIO interrupt
470 GPIO_INT7 GPIO interrupt
471 IPC_GR0 IPC interrupt generation
472 IPC_GR1 IPC interrupt generation
473 IPC_GR2 IPC interrupt generation
474 IPC_GR3 IPC interrupt generation
475 Reserved
476 Reserved
477 Reserved
478 Reserved
7.3.2 CIC Registers
This section includes the CIC memory map information and registers.
7.3.2.1 CIC0 Register Map
Table 7-26. CIC0 Registers
ADDRESS
OFFSET REGISTER MNEMONIC REGISTER NAME
0x0 REVISION_REG Revision Register
0x4 CONTROL_REG Control Register
0xC HOST_CONTROL_REG Host Control Register
0x10 GLOBAL_ENABLE_HINT_REG Global Host Int Enable Register
0x20 STATUS_SET_INDEX_REG Status Set Index Register
0x24 STATUS_CLR_INDEX_REG Status Clear Index Register
0x28 ENABLE_SET_INDEX_REG Enable Set Index Register
0x2C ENABLE_CLR_INDEX_REG Enable Clear Index Register
0x34 HINT_ENABLE_SET_INDEX_REG Host Int Enable Set Index Register
0x38 HINT_ENABLE_CLR_INDEX_REG Host Int Enable Clear Index Register
0x200 RAW_STATUS_REG0 Raw Status Register 0
0x204 RAW_STATUS_REG1 Raw Status Register 1
0x208 RAW_STATUS_REG2 Raw Status Register 2
0x20C RAW_STATUS_REG3 Raw Status Register 3
0x210 RAW_STATUS_REG4 Raw Status Register 4
116 Memory, Interrupts, and EDMA for 66AK2L06 Copyright © 2015, Texas Instruments Incorporated
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