66AK2L06
SPRS930 –APRIL 2015
66AK2L06 Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
1 66AK2L06 Features and Description
1.1 Features
1
– Packet Accelerator Enables Support for
• Four TMS320C66x DSP Core Subsystems (C66x
CorePacs), Each With
• 1 Gbps Wire Speed Throughput at 1.5
MPackets Per Second
– 1.0 GHz or 1.2 GHz C66x Fixed/Floating-Point
DSP Core
– Security Accelerator Engine Enables Support for
• 38.4 GMacs/Core for Fixed Point @ 1.2 GHz
• IPSec, SRTP, and SSL/TLS Security
• 19.2 GFlops/Core for Floating Point @ 1.2
• ECB, CBC, CTR, F8,CCM, GCM, HMAC,
GHz
CMAC, GMAC, AES, DES, 3DES, SHA-1,
SHA-2 (256-bit Hash), MD5
– Memory
• Up to 6.4 Gbps IPSec
• 32K Byte L1P Per CorePac
– Ethernet Subsystem
• 32K Byte L1D Per CorePac
• Four SGMII Port Switch
• 1024K Byte Local L2 Per CorePac
• Peripherals
• ARM CorePac
– Digital Front End (DFE) Subsystem
– Two ARM
®
Cortex
®
-A15 MPCore™ Processors
at Up to 1.2 GHz
• Support up to Four Lane JESD204A/B (7.37
Gbps Line Rate Max.) Interface to Multiple
– 1MB L2 Cache Memory Shared by Two ARM
Data Converters
Cores
• Integration of Digital Down/Up-Conversion
– Full Implementation of ARMv7-A Architecture
(DDC/DUC) Modules
Instruction Set
– IQNet Subsystem
– 32KB L1 Instruction and Data Caches per Core
• Transporting data streams to an integrated
– AMBA 4.0 AXI Coherency Extension (ACE)
Digital Front End (DFE)
Master Port, Connected to MSMC for Low
Latency Access to Shared MSMC SRAM
– Two One-Lane PCIe Gen2 Interfaces
• Multicore Shared Memory Controller (MSMC)
• Supports Up to 5 GBaud
– 2 MB SRAM Memory Shared by Four DSP
– Three Enhanced Direct Memory Access (EDMA)
CorePacs and One ARM CorePac
Controllers
– Memory Protection Unit for Both MSM SRAM
– 72-Bit DDR3 Interface, Speeds Up to 1600 MHz
and DDR3_EMIF
– EMIF16 Interface
• On-chip Standalone RAM (OSR) - 1MB On-Chip
– USB 3.0 Interface
SRAM for Additional Shared Memory
– USIM Interface
• Hardware Coprocessors
– Four UART Interfaces
– Two Fast Fourier Transform Coprocessors
– Three I
2
C Interfaces
• Support Up to 1200 Msps at FFT Size 1024
– 64 GPIO Pins
• Support Max FFT Size 8192
– Three SPI Interfaces
• Multicore Navigator
– Semaphore Module
– 8k Multi-Purpose Hardware Queues with Queue
– Fourteen 64-Bit Timers
Manager
• Commercial Case Temperature:
– Packet-Based DMA for Zero-Overhead
– 0ºC to 100ºC
Transfers
• Extended Case Temperature:
• Network Coprocessor
– -40ºC to 100ºC
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
