56 Primary Events
8 Secondary Events †
EDMA3
CC0
CIC0
ARM
INTC
56 Primary Events
8 Secondary Events
HyperLink
56 Primary Events
EDMA3
CC1
56 Primary Events
EDMA3
CC2
56 Primary Events
EDMA3
CC3
C66x
CorePac
38 Secondary Events
57 Primary Events
448 Primary Events
56 Primary Events
EDMA3
CC4
474 Events
8 Secondary Events †
8 Secondary Events †
8 Secondary Events †
8 Secondary Events †
† ARM shares two secondary events with every instance of EDMA.
4 Secondary Events
479 Events
32 Secondary Events †
CIC2
66AK2E
66AK2E05, 66AK2E02
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Figure 7-4. Interrupt Topology
Table 7-22 shows the mapping of primary events to C66x Corepac
Table 7-22. System Event Mapping — C66x CorePac Primary Interrupts
EVENT NO. EVENT NAME DESCRIPTION
0 EVT0 Event combiner 0 output
1 EVT1 Event combiner 1 output
2 EVT2 Event combiner 2 output
3 EVT3 Event combiner 3 output
4 TETB_HFULLINT0 TETB is half full
5 TETB_FULLINT0 TETB is full
6 TETB_ACQINT0 TETB acquisition complete interrupt
7 TETB_OVFLINT0 TETB overflow condition interrupt
8 TETB_UNFLINT0 TETB underflow condition interrupt
9 EMU_DTDMA Emulation interrupt for host scan, DTDMA transfer complete and AET
10 MSMC_MPF_ERROR0 Memory protection fault indicators for system master PrivID = 0 (C66x
CorePac)
11 Reserved Reserved
12 Reserved Reserved
13 IDMA0 IDMA channel 0 interrupt
14 IDMA1 IDMA channel 1 interrupt
15 SEM_ERR0 Semaphore error interrupt
16 SEM_INT0 Semaphore interrupt
17 PCIe_0_INT4 PCIe0 MSI interrupt
18 TSIP_RCV_FINT0 TSIP receive frame interrupt for channel 0
19 TSIP_XMT_FINT0 TSIP transmit frame interrupt for channel 0
20 TSIP_RCV_SFINT0 TSIP receive super frame interrupt for channel 0
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